A Three-Phase Reduced Switch Count Multilevel Inverter Topology

Figure 22

Experimental gating pulses for proposed three-phase topology. (a)–(d) Pulses for phase-R; (e) H-bridge pulses for phase-Y; (f) H-bridge pulses for phase-B.

(a)

(b)

(c)

(d)

(e)

(f)