A Three-Phase Reduced Switch Count Multilevel Inverter Topology

Table 1

Comparison between proposed and conventional single-phase topologies for “k” cells.

Multilevel inverter structure	Topology presented in [34]	CHB topology	Proposed
No. of voltage levels	(4 × k) + 1	(2 × k) + 1	(8 × k) + 1
Max. output voltage	(2 × k) × Vdc	(k) × Vdc	(4 × k) × Vdc
Main switches	(4 × k) + 4	(4 × k)	(8 × k) + 4
Gate drivers	(4 × k) + 4	(4 × k)	(6 × k) + 4
Max. device count in conduction path	(2 × k)	(2 × k)	(2 × k) + 2
SDCs	(2 × k)	(k)	(4 × k)
Total standing voltage on switches	(4 × k) × Vdc	(4 × k) × Vdc	(10 × k) × Vdc
Voltage-level generation part
Polarity reversal part	(8 × k) × Vdc		(16 × k) × Vdc