A Three-Phase Reduced Switch Count Multilevel Inverter Topology

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td class="align_left">Multilevel inverter structure</td><td class="align_center">Topology presented in [<a href="/journals/itees/2022/6193731/#B34" target="_blank">34</a>]</td><td class="align_center">CHB topology</td><td class="align_center">Proposed</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left">No. of voltage levels</td><td class="align_center">(4 × <i>k</i>) + 1</td><td class="align_center">(2 × <i>k</i>) + 1</td><td class="align_center">(8 × <i>k</i>) + 1</td></tr><tr><td class="align_left">Main switches</td><td class="align_center">3 × ((4 × <i>k</i>) + 4)</td><td class="align_center">3 × ((4 × <i>k</i>))</td><td class="align_center">3 × ((8×<i>k</i>) + 4)</td></tr><tr><td class="align_left">Gate drivers</td><td class="align_center">3 × ((4 × <i>k</i>) + 4)</td><td class="align_center">3 × ((4 × <i>k</i>))</td><td class="align_center">3 × ((6 × <i>k</i>) + 4)</td></tr><tr><td class="align_left">SDCs</td><td class="align_center">3 × (2 × <i>k</i>)</td><td class="align_center">3 × (<i>k</i>)</td><td class="align_center">(4 × <i>k</i>)</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

<div>Comparison between proposed and conventional three-phase topologies for “<i>k</i>” cells.</div>

International Transactions on Electrical Energy Systems

A Three-Phase Reduced Switch Count Multilevel Inverter Topology

Table 2