Design and Analysis of a New Coupled Inductor-Based Interleaved High Step-Up DC-DC Converter for Renewable Energy Applications

Abstract

In this paper, a novel nonisolated interleaved high step-up DC-DC converter is proposed based on the coupled inductor and voltage multiplier cell (VMC) methods. Due to the interleaved structure, its input current ripple is low. The low input current ripple and also high power efficiency make the proposed converter suitable for renewable energy applications like photovoltaic (PV) and fuel cell (FC) power generation systems. The windings of the coupled inductors are combined with VMCs to further increase the output voltage with a low power switch’s duty cycle. This combination also leads to obtaining a flexible voltage gain that can be adjusted by coupled inductors’ turns ratio and power switches’ duty cycle. The voltage peaks over semiconductors are much lower than the output voltage. Therefore, low-rated semiconductors can be used for the implementation of the proposed converter, which can reduce the cost and volume. Generally, high voltage gain, low voltage, current stress of power switches, low input current ripple, high efficiency, common ground between the input and output ports, and a low number of elements are the main benefits of the suggested structure. The operation principle, steady-state analysis, and comparison with other converters are presented to show the advantages of the suggested converter. Also, a prototype is built, and the experimental results are presented to prove the theoretical analysis. This prototype is implemented with 200 W rated power, 25 V∼400 V voltage conversion, and 50 kHz switching frequency. Additionally, the efficiency is measured at 95.3% at the rated power.

1. Introduction

1.1. Contextualization

In recent years, renewable energy sources like photovoltaic (PV), wind turbines, and fuel cells (FCs) have been significantly grown in DC microgrids and other industrial applications. These sources benefit from pollution-free and high-scale usage ability [1, 2]. Also, the overuse of fossil fuels leads to a remarkable concern about global warming. Renewable energy sources are introduced as a suitable alternative to fossil fuels and can help to improve environmental pollution [3, 4]. However, renewable energy sources suffer from drawbacks, such as low voltage levels (typically lower than 50 V). Thus, to form a proper connection between these sources and a high voltage DC-bus, a high step-up DC-DC converter with a high voltage conversion ratio is indispensable [5, 6]. The high-voltage DC-bus can be connected to a DC microgrid, three- and single-phase inverters, and other loads that need high voltage [7]. The classical boost DC-DC converter is one of the options to overcome the abovementioned problems of renewable energy sources [8]. This topology of DC-DC converters benefits from a simple design, modeling, and implementation, low cost, volume, and a number of components [9]. However, it has a low voltage conversion ratio and high peak voltage of semiconductors. On the other hand, to increase the output voltage, the duty cycle of the power switch should be set at a higher value [10]. Therefore, the condition loss is increased and the power efficiency is reduced. High voltage gain converters are presented to solve this challenge. The techniques for voltage gain increment can be classified into switched capacitors (SCs), switched inductors (SIs), magnetic coupling including coupled inductors and transforms (built-in and isolated), voltage multiplier cells (VMCs), and multistage structures [11]. Additionally, high step-up converters have different types as follows: nonisolated or isolated, voltage or current fed, bidirectional or unidirectional, minimum or nonminimum phase, soft or hard switched, and multiinputs/outputs or single ports topologies.

1.2. Related Works and Literature Review

Nonisolated boost topologies are proposed in Refs. [12, 13], for renewable energy usages with VMCs and coupled inductors. These converters benefit from continuous input current with low ripple, low voltage stress over switches and didoes, low components count, and higher efficiency. However, to attain a high voltage gain, the number of coupled inductor’s turns ratio and the switch’s duty cycle must be set at a high value, which is the main drawback of theirs. A two-input high voltage conversion converter is suggested in Ref. [14]. It is proper for PV systems. This topology can deliver power to the load from different power supplies. However, it cannot operate with two different voltage level input sources. The voltage spike across the power switch is high. A VMC-based multiinput multioutput structure is presented in Ref. [15]. A power switch and one magnetic core are needed to increase the number of ports, which is the main drawback of this topology. An interleaved boost structure with VMCs and coupled inductor is suggested in Ref. [16]. This converter can connect a PV panel to a high-voltage DC-bus. Despite this, a high number of capacitors and diodes are used to increase the output voltage. A dual-input single-output topology with ultra high voltage gain is suggested in Ref. [17], for high-voltage applications. This topology suffers from high input current ripple, and for renewable energy usages, it needs a low-pass filter for each input port. Three-winding coupled inductor-based converters with a high voltage gain, and low voltage stress features are suggested in Refs. [18–20]. The input current ripple is high, and there is no common ground between input and output ports. Interleaved converters using coupled inductors and built-in transformers are suggested in Refs. [21, 22], for photovoltaic systems. The advantages of these topologies are high voltage gain, low peak voltage of power switches, and low input current ripple. However, the components count of them is higher than the other converters.

1.3. Contribution and Novelty

In this paper, a new structure of interleaved high step-up converter is suggested for renewable energy usages like PV and FC systems. The coupled inductor and VMC approaches are used in conjunction to improve the voltage conversion ratio while minimizing peak voltage over power switches. The voltage conversion ratio is controlled by two different parameters. Indeed, it can be increased by the turns ratio of the coupled inductors and the duty cycle of the power switches. Therefore, an adjustable voltage gain is obtained. The voltage stresses across the power switches and diodes are much lower than the output voltage. Because of low voltage stress, low-rated power switches can be implemented. Thus, power losses and the cost of the converter are decreased. The other benefits of the presented topology are low input current ripple, high efficiency, and common ground between input and output ports. The operation principle, steady-state analysis, and comparison with other similar structures are provided to show the advantages of the suggested structure. A 200 W prototype with 25–400 V voltage conversion is built, and the experimental results are presented to prove the theoretical analysis. Additionally, the efficiency is measured at 95.3% at the rated power. In Table 1, a qualitative comparison is provided between the reviewed papers and the proposed converters.

Table 1 

Qualitative comparison between the reviewed papers and the proposed converters.

2. Suggested Structure and Operational Analysis

The circuit of the proposed interleaved high step-up converter includes two power MOSFET (S₁ and S₂), five power diodes (D₁∼D₅), five capacitors (C₁∼C₄ and C_o), and three coupled inductors. Each coupled inductor consists of two winding with one magnetic core. Diodes D₁ and D₂ along with capacitors C₁ and C₂ form the first VMC stage. The increased voltage by this VMC is dropped across capacitor C_o. The secondary side of the coupled inductors is combined with other VMC including diodes D₄ and D₅ and capacitors C₃ and C₄. This combination leads to a further increase in the output voltage. Indeed, with the increasing turns ratio number of the used coupled inductors, the voltage gain extremely increased. Thus, without a higher duty cycle value, high voltage at the output port is obtained. The coupled inductors are assumed as ideal transformers with magnetizing inductance (L_m) and leakage inductance (L_k).

The turns ratio number of the coupled inductor is defined in (1). Furthermore, to illustrate the leakage effect, the coupling coefficient (k) is considered as (2). The configuration of the suggested topology is depicted in Figure 1. Also, the primary waveforms are depicted in Figure 2. The switching period is defined as T_s = 1/f_s, and there are four operation modes in each T_s. It should be

Figure 1 

The presented DC-DC converter.

Figure 2 

The main waveforms.

noticed that, in each operation mode, using KCL and KVL lows, the equations are calculated.

Mode 1 & 3 [t₀ < t < t₁] & [t₂ < t < t₃]: modes 1 and 3 have an almost equal operation. During these modes, power switches S₁ and S₂ are turned ON. The magnetizing (L_m1 and L_m2) and leakage (L_k1 and L_k2) inductances are charged by input voltage V_in. Therefore, their currents are increased linearly. Diodes D₂ and D₄ are forward-biased and other diodes are turned OFF. Due to the forward bias of diode D₂, capacitor C₂ is discharged, and its energy along with the leakage energy of L_k3 is transferred to the capacitor C₁. The coupled inductors’ secondary sides charge capacitor C₃, and capacitors C₄ and C_o are discharged to the load. The configuration of modes 1 and 3 is depicted in Figure 3(a). Using KVL and KCL lows, the following relations are achieved in these modes:

(a)

(b)

(c)

Figure 3 

The equivalent circuits of modes (a) 1 & 3, (b) 2, and (c) 4.

Mode 2 [t₁ < t < t₂]: at t = t₁, power switch S₂ is turned OFF and power switch S₁ is still turned ON. Thus, the current of L_m1 and L_k1 continues to increase. On the other hand, their currents are decreased due to the negative voltage across L_m2 and L_k2. The situations of all diodes are the same as modes 1 and 3. The stored energy of L_k1 and L_k2 is transferred to the output side through the secondary windings of the coupled inductors. Also, the leakage energy of L_k3 charges the capacitor C₁. As a result, the leakage energy is recycled. This mode ends when power switch S₂ is turned ON at t = t₂. The configuration of mode 2 is depicted in Figure 3(b). Based on this configuration, the subsequent equations are calculated as follows:

Mode 4 [t₃ < t < t₄]: the configuration of this mode 4 is illustrated in Figure 3(c). This mode starts when power switch S₁ is turned OFF. At the beginning of the mode, diodes D₁, D₃, and D₅ are forward-biased. The currents of L_m1 and L_k1 are decreasing linearly. However, the magnetizing and leakage inductances L_m2 and L_k2 are charged by V_in. The energy of capacitor C₁ charges the capacitor C_o through diode D₃. Also, capacitor C₂ is charged by the leakage energy of L_k1. Also, the current direction of capacitor C₂ is the same as the current of diode D₁. The stored energy of the coupled inductors’ secondary windings is transferred to the load by diode D₅. During this mode, capacitor C₃ is discharged, and capacitor C₄ is charged. The following equations are achieved in mode 4:

3. Steady-State Analysis

This part provides steady-state analysis, including voltage conversion ratio, voltage stress, and current calculations. To determine the voltage gain, first, the capacitors’ voltages are obtained based on the volt-second balance principle on magnetizing inductances L_m1, L_m2, and L_m3. The coupling coefficient (k) of leakage inductances L_k1, L_k2, and L_k3 are also considered.

3.1. Voltage Calculation

Applying the volt-second balance principle on L_m1, the following equation is achieved:

By simplifying (19), the voltage of capacitor C₂ can be expressed as follows:

Considering (8), the voltage of capacitors C₁ and C₂ are equal as follows:

Replacing (20) and (21) into (14), the voltage of capacitor C_o can be found as follows:

V_C3 and V_C4 are presented at (23) and (24). The voltage of capacitor C₃ can be calculated at mode 2 when diode D₄ is turned ON. This voltage is obtained based on voltages of coupled inductors’ secondary sides. The same method is taken to calculate V_C4 at mode 4. Finally, using (7), the voltage gain can be obtained as (24). The voltage stresses of diodes D₁, D₃, D₅, and power switch S₂ can be attained at mode 2. These equations are summarized in Table 2.

Table 2 

The obtained voltage stresses at mode 2.

Also, the voltage stresses of diodes D₂ and D₄, and power switch S₁ can be attained at mode 4.

Figures 4 and 5 show the voltage gain and normalized voltage stresses, respectively. For equal duty cycle values, the voltage gain is enhanced by increasing N. Thus, the voltage gain is more flexible and can be controlled by two diverse parameters. As a result, for high-voltage applications, a low-duty cycle can be selected. The maximum voltage stress across semiconductors is related to diodes D₄ and D₅, which its value is 0.68 for k = 1, D = 0.6, and N = 1.

Figure 4 

The voltage gain (M) versus N, D, and k.

Figure 5 

The voltage stress across the semiconductors (for k = 1 and D = 0.6).

3.2. Current Calculation

Using the voltage gain relation, the average input current can be written versus the output current as follows:

The average current of switches S₁ and S₂ are equal to the average currents of L_m1 and L_m2.

Considering (30), the input current is equally shared between different phases. According to the proposed converter’s configuration, the average currents of the diodes are equal to the output current.

The current stresses of the semiconductors are obtained based on the average currents and summarized in Table 3. When power switch S₁ is turned ON, the current of diode D₂ is passed from L_m3. Therefore, the following equation can be expressed as

Table 3 

The semiconductor currents in each mode.

Also, when power switch S₁ is turned OFF, the current of L_m3 is obtained as follows:

Thus, the average current of L_m3 can be written as follows (33):

The current of the capacitors can be calculated based on the didoes current. These currents are summarized in Table 4.

Table 4 

The capacitor’s current.

4. Design Considerations

This part presents the design equations of the coupled inductors and capacitors.

4.1. Magnetizing Inductances

To achieve continuous conduction mode (CCM) operation, the minimum values of the magnetizing inductances L_m1 and L_m2 are calculated based on the following equations:

Thus, the minimum values of L_m1 and L_m2 are calculated as follows:

Also, the minimum value of L_m3 is attained as follows (36):

4.2. Capacitors

To minimize the voltage ripple across the capacitors, the following relation is assumed:

Using the calculated voltages and currents, the minimum values of C₁∼C_o are found as follows:

5. Comparison Study

This part presents a comparison between the presented interleaved topology and other similar DC-DC structures. The summary of this section is given in Table 5. In this comparison, the number of components, common ground, used technology to enhance the output voltage, and maximum peak voltage over semiconductors is considered. The voltage gain comparison versus diverse values of duty cycle (0.2 < D < 0.8) and turns ratio number (1 < N < 5) are shown in Figures 6(a) and 6(b), respectively. According to these figures, the voltage conversion ratio of the recommended topology versus is higher than the others. Therefore, the suggested structure uses lower power switches’ duty cycle and coupled inductors’ turns ratio for the equal output voltage. The converter in [7] has a higher number of components, which uses 14 diodes and 6 power switches. Thus, its cost is high. The converters in [4, 8], and the presented converter have a lower number of components than the introduced converters in Table 5. Thus, the proposed topology obtained a higher output voltage with a low number of elements. A comparison of the normalized maximum peak voltage of diodes and power switches is depicted in Figures 7(a) and 7(b), respectively. The structure in [16] has lower maximum voltage stress across diodes. However, this topology suffers from the absence of common ground between input and output ports. For the same value of the voltage gain, it needs a higher duty cycle and turns ratio to achieve a high output voltage, compared with the recommended topology. Also, according to the steady-state analysis, in the suggested structure, the voltage stress on diodes D₄ and D₅ is high and other didoes have low voltage stress. For 1 < N < 3, the peak voltage over power switches in the suggested topology and [22] is lower than others. For N = 1, V_S/V_o of the suggested topology and [22] are equal to 0.18 and 0.2. Thus, low-rated power switches can be implemented in these topologies. Considering the results of the comparison, the proposed interleaved topology has a high voltage gain with a reduced peak voltage of the power switches, and it benefits from the common ground among input and output ports.

Table 5 

Summary of the comparison results.

(a)

(b)

Figure 6 

Comparison, (a) voltage gain versus D and N = 1and (b) voltage gain versus N and D = 0.6.

(a)

(b)

Figure 7 

Comparison, (a) V_D/V_o and (b) V_S/V_o.

6. Results and Discussion

This part presents the experimental results of the suggested topology. The specifications of the proposed topology are given in Table 6. The experiment prototype is built with 25∼400 V voltage conversion, P_o = 200 W, and f_s = 50 kHz. The duty cycles of the power switches are 0.6, and the turns ratio of the coupled inductors is taken equal to 1. The experimental waveforms of power switch S₁ and S₂ are depicted in Figures 8(a) and 8(b).

Table 6 

The suggested converter’s specifications.

(a)

(b)

Figure 8 

Experimental waveforms, (a) V_S1 & i_S1, (b) V_S2 & i_S2.

The voltage and current of switch S₁ are obtained at 61 V and 6 A. Also, the voltage and current of switch S₂ are measured at 73 V and 5.8 A. The voltages and currents of diodes D₁∼D₅ are shown in Figures 9(a)–9(e). According to Figure 9(a), the peak voltages of diode D₁, D₂, and D₃ are measured at 61 V, 61 V, and 61.3 V, respectively. Thus, equation (27) is verified by these results. On the other hand, the peak currents of didoes D₁, D₂, and D₃ have obtained at 2 A, 3 A, and 1.98 A. The measured voltage stress of diodes D₄ and D₅ is 268 V. Therefore, equation (28) is proved. The peak current of diodes D₄ and D₅ are measured at 1.5 A and 2.1 A. These experimental results can verify the presented equations in Table 2. The experimental waveforms of the capacitor’s voltages and output voltage (V_o) are depicted in Figure 10.

(a)

(b)

(c)

(d)

(e)

Figure 9 

Experimental results of diodes, (a) D₁ (b) D₂, (c) D₃, (d) D₄, and (e) D₅.

(a)

(b)

(c)

(d)

(e)

(f)

Figure 10 

Experimental results, (a) V_o, (b) V_C1, (c) V_C2, (d) V_C3, (e) V_C4, and (f) V_Co.

V_o of the recommended topology is obtained 390 V. Therefore, the experimental voltage conversion ratio is obtained equal to 15.6. It should be noticed that the theoretical voltage gain is achieved at 16 for N = 1 and D = 0.6. The voltages of capacitors C₁ and C₂ are measured at 60 V and 61 V. Also, according to equation (21), the theoretical values of V_C1 and V_C2 are equal. The voltage of capacitor C₃ is shown in Figure 10(c). This result verifies equation (23). Additionally, the voltage waveforms of capacitors C₄ and C_o are shown in Figures 10(e) and 10(f), respectively. V_Co and V_C4 are measured at 122 V and 121 V, which verify equations (22) and (24). The theoretical and experimental values of the semiconductors and capacitors voltages and the output voltage are compared and presented in Table 7. The input current waveform is depicted in Figure 11.

Table 7 

The experimental and theoretical comparison.

Figure 11 

The input current (i_in) experimental waveform.

The average value of the input current is measured at almost 8.15 A with 0.9 A peak-to-peak current. Therefore, the recommended topology has an input current with reduced ripple, and it can be useful for PV and other renewable power generations. The measured efficiency of the suggested converter versus output power is shown in Figure 12. As can be seen in this figure, the maximum efficiency is obtained at P_o = 120 W which is equal to 95.96%. Also, at rated power (P_o = 200 W), efficiency is measured 95.3%.

Figure 12 

The measured efficiency curve.

7. Conclusion

This paper proposes a novel nonisolated interleaved high step-up DC-DC converter based on coupled inductor and voltage multiplier cell (VMC) methods. Due to the interleaved structure, its input current ripple is low. The low input current ripple and also high power efficiency make the proposed converter suitable for renewable energy applications like photovoltaic (PV) and fuel cell (FC) power generation systems. The windings of the coupled inductors are combined with VMCs to further increase the output voltage with a low power switch’s duty cycle. This combination also leads to obtaining a flexible voltage gain that can be adjusted by coupled inductors’ turns ratio and power switches duty cycle. The voltage peaks over semiconductors are much lower than the output voltage. Therefore, low-rated semiconductors can be used for the implementation of the proposed converter, which can reduce the cost and volume. (1) High voltage gain, (2) low voltage and current stress of power switches, (3) low input current ripple, (4) high efficiency, (5) common ground between the input and output ports, and (6) a low number of elements are the main benefits of the suggested structure. The operation principle, steady-state analysis, and comparison with other converters are presented to show the advantages of the suggested converter. Also, a prototype is built, and the experimental results are presented to prove the theoretical analysis. This prototype is implemented with 200 W rated power, 25 V∼400 V voltage conversion, and 50 kHz switching frequency. Additionally, the efficiency is measured at 95.3% at the rated power.

Data Availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.