Abstract

Modular multilevel converters (MMCs) are widely applied to medium and high voltage occasions. The total power consumption of the submodule (SM) and the maximum power consumption of power devices in the SM are related to the operating costs and lifetime of the MMC. Existing literature only considers total power loss optimization or maximal power consumption optimization in MMC’s SM. In this article, a reduced loss and extended lifetime power loss optimum control (RLEL-PLOC) is introduced to inject the first-best second harmonic circulation into the MMC’s arm current. Compared with the conventional power loss optimization control, the proposed control could decrease the maximal power consumption of the semiconductor devices without increasing the total loss of the SM. According to study results of the MMC, compared with the circulating current suppression control (CCSC) method, the total power consumption of the SM could be reduced by 4.2% and the maximal power dissipation in the SM could be reduced by 5.4% with RLEL-PLOC. PSCAD simulation and MMC prototype experiment are also carried out, and the research results verified the availability of the put forward RLEL-PLOC for MMCs.

1. Introduction

Modular multilevel converters (MMCs) were put forward by A. Lesnicar at the beginning of the 21st century [1, 2]. Recently, MMCs have attracted widespread attention from multiple industries because of its superiorities of modularization, relatively low power dissipation, better power quality, and convenient scalability [3, 4]. The modular multilevel converter plays a significant role in the occasions of energy storage, drive systems for hydrogen fuel cell compressor motors, and renewable energy grid connection [5].

The MMC is composed of numerous submodules (SMs), each of which contains multiple power devices. Power loss in these power devices constitutes a significant part of operating costs [6, 7]. Therefore, decreasing the total energy loss is essential for the MMC’s economical operation [8, 9]. The maximal power consumption of the semiconductor devices would affect the lifetime of MMCs [10, 11].

Currently, the existing methods to optimize power loss for MMCs are mainly divided into three types: the SM devise majoritization-based technique, the switching frequency diminution-based technique, and the circulation dominate-based technique. Reference [12] proposes an SM with a shunt group diode with inferior conduction voltage descent to optimize the MMC’s loss. References [13, 14] propose an SM with an inferior conduction voltage descend power devices that can optimize the MMC’s power loss. However, the SM devises the majoritization-based technique to increase the system design complexity.

Reducing the switching frequency can also optimize the power loss of MMCs. References [15, 16] present a capacitor voltage equilibrium technology to lower the power consumption at low-switching frequency. Reference [17] brings in a mixed pulse width modulation (PWM) which can operate with the one-time frequency modulation method of part SMs to optimize power loss. However, the low switching frequency would affect the MMC’s output current wave.

Circulating current control is widely adopted in the power loss optimization of MMCs. Reference [9] proposes an optimization method to control the SM’s power consumption and the SM’s capacitor voltage fluctuation value of MMC by adjusting the second harmonic circulation current (SHCC). Literature [18] presents a circulating current suppression control (CCSC) method to optimize the power loss by eliminating the SHCC of MMC’s arm current. Literature [19] presents an SHCC control method to reduce the submodule capacitance value and the power consumption provoked by the SHCC injection. Reference [20] presents an SHCC control method by decreasing the MMC arm current’s maximum value to decrease the power consumption of MMCs. Literature [21] introduces an SHCC control technique by controlling the current rating of semiconductor devices to optimize MMC’s power loss. Literature [22] proposes a power consumption majoritization control in view of the infusion of the supreme second harmonic circulation current into MMC’s arm current to decrease MMC’s power loss. Literature [23] puts forward a power consumption majoritization dominant to improve the power consumption in SMs. However, the circulating current dominate-based technology either only considers the total power loss optimization and neglects the maximal power consumption optimization in SMs or only considers the maximum power loss optimization, and the total power consumption optimization is not considered. Simply combining the abovementioned methods cannot optimize the total loss and maximum loss at the same time.

In conclusion, the SM devise majoritization-based technique can optimize the MMC’s power loss, while increasing the system design complexity. Reducing the switching frequency can also optimize the power loss of MMCs, but the low switching frequency would affect the MMC’s output current wave. This paper proposes a multitarget power loss optimum control (RLEL-PLOC) by inpouring first-best second harmonic circulation into the bridge arm. The contribution of this paper can be summarized as follows:(1)The proposed RLEL-PLOC can achieve total power loss optimization and maximal power dissipation optimization in SMs, which can improve the energy transmission efficiency to reduce the operating costs of the MMC and reduce the power loss stress of the semiconductor device with the maximum power dissipation in SMs to improve the lifetime of MMCs simultaneously.(2)Using the circulating current control to optimize the power loss of MMCs to avoid increasing the system design complexity and reducing the switching frequency would affect the MMC’s output current wave.(3)Compared with CCSC, capacitor voltage ripples could be reduced under most operating conditions with the proposed RLEL-PLOC, which can improve the economy and portability of the MMC.

The other parts of the article are arranged as follows. Part II represents the MMC including the formation of MMCs and the circulating current of MMCs. Part III puts forward the RLEL-PLOC for MMCs. Sections IV and V introduce the simulation and experimental research of MMCs, respectively, to verify the RLEL-PLOC. In the end, Part VI proposes the summary.

2. Descriptions of MMCS

2.1. Composition of the MMC

The principal collocation of the MMC is displayed in Figure 1(a), including 6 arms. Each arm is made up of n tantamount submodules and an inductance, . Figure 1(b) demonstrates the i-th (i = 1, 2, …, n) submodule in phase A’s upper arm, which contains the switch/diode (/, 1/), and the capacitor [24]. Normally, the i-th drive signal controls the i-th SM as

As is displayed in Table 1, there are two statuses of the submodule, which are “On” status and “Off” status. Once Si = 1, the submodule is in “On” and the export voltage is equivalent to the voltage uci. When  = 0, the submodule is in “Off” and equals 0. In the “On” status, the charge or discharge of the SM capacitor is regulated by the bridge arm’s current direction. As seen in Figure 1(b), Under the “On” status, if bridge arm current iau > 0, the electric capacity is charged, increasing the voltage uci, and if iau < 0, the capacitor discharged, resulting in abate of the capacitor voltage uci. In the “Off” status, the relevant capacitor is by way, and voltage uci keeps constant, despite the bridge arm current direction [23, 24].

2.2. Circulating Current of the MMC

In case the power grid voltage latitude and phase position are and 0, the power grid’s current iga in the A phase iswithwhere denotes grid current latitude, φ denotes grid power factor angle, P denotes grid active power, Q denotes grid reactive power, and ω denotes the fundamental angular frequency.

Phase A’s arm current could stand for aswhere and ial are the current of the upper bridge arm and lower bridge arm. i2fa is phase A’s second harmonic circulation, which could be described aswhere and are the latitude and phase position of the . is the direct current (DC) side current and can be described aswhere is the dc-link voltage.

3. Proposed Multitarget Power Loss Optimal Strategy for the MMC

3.1. Power Loss in the SM

The power loss in three-phase MMC is majorly produced by the switches (/) and the diodes (/), including the on-state loss and switching loss [6]. Table 2 describes the on-state situation of the power devices in the i-th SM [23].(1)Once  < 0 and is 1, the runs past and ’s current is  = −. In other situations,  = 0. Therefore, the conduction loss PT1_con of iswhere and are on-state zero-current collector-emitter voltage and on-state collector-emitter resistance for the switch, respectively. T is the fundamental cycle and T = 2π/ω.(2)Once  > 0 and i is 1, the runs past and ’s current is is equal to . In other situations,  = 0. Therefore, the conduction loss PD1_con of iswhere and are on-state zero-current voltage drop and on-state resistance for the diode, respectively.(3)Once  > 0 and is 0, the runs past and ’s current is equal to . In other situations,  = 0. Therefore, the conduction loss PT2_con of is(4)Once  < 0 and is 0, the runs past and ’s current is is equal to-. In other situations,  = 0. Therefore, conduction loss PD2_con of is

The switching loss of power devices comprises the open power consumption and shutoff power consumption of the switch and the opposite recovery power consumption of the diode. Table 3 shows the switching circumstances of the power device in SMs.(1)Once  > 0 and varies from 1 to 0, the diode shuts off and the switch opens. The reverse-recovery loss PD1_rec and open loss PT2_on arewhere is the opposite-recovery capacity of the diode and is the open capacity of the switch. is the submodule capacitor voltage mean value, and is the test voltage in the manufacturer’s manual.(2)Once iau > 0 and varies from 0 to 1, the opens and the shuts off. The turn-off loss PT2_off can be described aswhere is the shutoff capacity of the switch.(3)Once iau < 0 and varies from 1 to 0, the diode opens and the switch shuts off. The turn-off loss PT1_off could be described as(4)Once iau < 0 and varies from 0 to 1, the diode shuts off and the switch opens. The reverse-recovery loss PD2_rec and turn-on loss PT1_on could be described as

The total power loss PT1, PD1, PT2, and PD2_ of the , , , and can be expressed as

The total power consumption Ploss of the SM can be written as

Figure 2 describes the power consumption of the semiconductor power devices in the MMC’s SM running with the various operating conditions φ, wherein the CCSC [18] is employed. The Infineon power device module FZ750R65KE3 is employed in MMCs. The power consumption of semiconductor devices in SMs can be calculated based on (7)–(15) [25]. In Figure 2, the power consumption of semiconductor power devices in the SM trans with the alter of power operating conditions φ.

Figure 3 describes the power consumption in the SMs, where the CCSC is employed. The total power consumption Ploss in the SM could be calculated according to (16). In Figure 3, the total power consumption Ploss of the SM trans along with the trans of operation conditions.

3.2. Proposed Multitarget Power Loss Optimization Method

As shown in Figure 4, this paper proposes RLEL-PLOC for the MMC, which can largely decrease the maximal power consumption of the semiconductor devices in SMs without increasing the total power consumption of the submodule. This method will inject the first-best second harmonic current into the MMC’s bridge arm, for the sake of improving the efficiency and lifetime of the MMC.

At an assigned P and Q, the and φ could be derived in view of (3) and the grid current iga could be derived in view of (2). The DC side current idc could be derived according to (6). In Figure 4, multifarious i2fa is thought of with diverse latitude and phase position pairs (I2fm, θ2f) of the second harmonic current. In every pair of (I2fm, θ2f), according to (4), we can obtain the upper arm current iau. The power loss PT1, PD1, PT2, and PD2 and the total power loss Ploss could be calculated in view of (7)–(16). The maximum power loss PSmax = Max(PT1, PD1, PT2, PD2) in the SM can be obtained under each pair of (I2fm, θ2f). The RLEL-PLO algorithm needs to be satisfiedwhere Ploss_CCSC is the SM’s total power loss with CCSC. In (17), we minimize the power loss set (PSmax set), meanwhile making the [Ploss set] not exceed Ploss_CCSC. According to the constraint conditions shown in Figure 4, the optimal second harmonic circulation reference values (I2fm_ref, θ2f_ref) that meet the conditions can be obtained by mathematically solving (17).

3.3. Proposed Multitarget Optimization Control

Figure 5 describes the MMCs’ RLEL-PLOC which is proposed. Figure 5(a) represents the MMCs’ P control and Q control [25], where the dq frame components of the grid current and voltage are , and , , respectively. The filtered inductance of the grid is . The voltage phase angle of the grid side is . The id_ref and iq_ref, are the current references yielded by the given P and Q conditions. Then, ua_ref, ub_ref, and uc_ref are the voltage references emerged according to the complex dominant method of power grid current.

Figure 5(b) describes the calculation of the dq frame component under the circulation references id_2f_ref and iq_2f_ref conditions. Under the given power conditions, the optimum amplitude and phase angle (I2fm_ref, θ2f_ref) of circulating current reference under the second-order harmonic condition could be obtained according to the RLEL-PLOC. Moreover, the circulating current references I2fa_ref, I2fb_ref, and I2fc_ref of three-phase second harmonic circulation could be acquired, respectively. Afterward, the dq frame component of id_2f_ref and iq_2f_ref under the second-order harmonic condition could be calculated by park transform under the three-phase condition for I2fa_ref, I2fb_ref, and I2fc_ref.

Figure 5(c) describes the circulating current’s complex control. Each phase’s arm currents are turned by the bandpass filter (BPF) to acquire the circulating current i2fa, i2fb, and i2fc of the second-order harmonic circulating current. Then, according to the park transform for three-phase to obtain id_2f of the d-axis component and iq_2f of the q-axis component. The vector control can deduce the voltage reference values ua_2f_ref, ub_2f_ref, and uc_2f_ref.

Figure 5(d) describes the upper arm yuj_ref  and lower arm ylj_ref  in phase j’s reference signals which are derived from 2(-uj_ref+  uj_2f_ref)/Vdc to 2(uj_ref  +  uj_2f)/Vdc, respectively. As is shown in Figure 5, the presented control could achieve total power dissipation optimization and the highest power dissipation optimization of the SM simultaneously.

3.4. Discussion of Put Forward RLEL-PLOC

Figure 6(a) illustrates the semiconductor devices’ power loss with assorted power factor angle φ. Figure 6(b) elaborates the SM’s total power dissipation in the MMC in a different power factor angle φ. Through Figure 6(a), it is noteworthy that the maximal power dissipation in SMs is efficaciously lowered by the RLEL-PLOC which is proposed under the whole running status. From Figure 6(b), it can be noticed that the proposed RLEL-PLOC has lower SM’s total power loss in contrast with CCSC under all operating conditions.

Figures 7(a)7(e) describe power loss under the proposed RLEL-PLOC of the T1, T2, D1, D2, and Ploss of MMCs, where the MMC operates at φ = 0. As is demonstrated in Figure 7, the power loss PT1, PT2, PD1, PD2, and Ploss changes along with the second harmonic circulation’s change and T2 has the maximal power dissipation among the semiconductor devices. Compared with the CCSC, the maximal power loss of T2 is largely decreased by the RLEL-PLOC with the most appropriate point (I2fm, θ2f) as (132, 4.84). Meanwhile, compared with the CCSC, the SM’s whole power loss is largely decreased by the RLEL-PLOC with the first-best point (I2fm, θ2f) as (132, 4.84).

Figures 8(a)8(e) describe the power loss under the proposed RLEL-PLOC of the T1, T2, D1, D2, and Ploss of MMCs, where the MMC operates at inverter pattern under φ = π. As is shown in Figure 8, the power loss of the T1, T2, D1, D2, and Ploss trans along with the second harmonic circulation current’s change and T1 has the maximal power dissipation among the semiconductor devices. Compared with the CCSC, the maximal power loss of T1 is largely decreased by the RLEL-PLOC with the most appropriate point (I2fm, θ2f) as (184, 1.76). Meanwhile, compared with the CCSC, the SM’s whole power loss is largely decreased by the RLEL-PLOC with the first-best point (I2fm, θ2f) as (184, 1.76).

4. Simulation Studies

As is shown in Figure 9, the simulation studies of the MMC are accomplished by applying the software of PSCAD to confirm the availability of the put-forward RLEL-PLOC. The major simulation arguments are shown in Table 4.

4.1. MMCs Operating at φ = 0

Figure 10 represents the simulation results of the MMC operating at φ = 0 in four dominant approaches comprising with CCSC method, with the RLEL-PLOC method, with literature 23’s method, and with literature 22’s method. Figure 10(a) describes the currents iau, ibu, and icu in the arm in the MMC with the CCSC method. Figure 10(b) describes the MMC’s grid current iga, igb, and igc under the CCSC method. Figure 10(c) represents the iau, ibu, and icu of MMCs under the RLEL-PLOC method. Figure 10(d) represents MMC’s grid current iga, igb, and igc of the under RLEL-PLOC method. Figure 10(e) represents the iau, ibu, and icu of MMCs the under literature 23’s method. Figure 10(f) represents MMC’s grid current iga, igb, and igc of the under literature 23’s method. Figure 10(g) represents the iau, ibu, and icu of MMCs under the literature 22’s method. Figure 10(h) represents MMC’s grid current iga, igb, and igc of the under literature 22’s method. Figure 10(i) displays the power dissipation and total power dissipation in SMs of the MMC with the CCSC method, with the RLEL-PLOC method, with literature 23’s method, and with literature 22’s method. It could be noticed that compared with the CCSC method, the maximum power loss of T2 of the RLEL-PLOC method is reduced by 2.5% from 3224 W to 3144W, and Ploss is reduced by 4.4% from 5646 W to 5397 W. It also could be noticed that compared with the RLEL-PLOC method, although the maximum power loss of T2 of the literature 23’s method is reduced by 0.7% from 3144W to 3122W, Ploss is increased by 5.1% from 5397 W to 5671 W. Compared with the RLEL-PLOC method, although Ploss of the literature 22’s method is reduced by 1.2% from 5397 W to 5334 W, the maximum power loss of T2 of the literature 22’s method is increased by 2.1% from 3144 W to 3209 W.

4.2. MMCs Operating at φ = π

Figure 11 represents the simulation results of modular multilevel converters operating at φ = π in four dominant approaches comprising with the CCSC method, with the RLEL-PLOC method, with the literature 23’s method, and with the literature 22’s method. Figure 11(a) describes the MMC’s iau, ibu, and icu with CCSC. Figure 11(b) describes the MMC’s grid current iga, igb, and igc with CCSC. Figure 11(c) illustrates the MMC’s iau, ibu, and icu of under RLEL-PLOC. Figure 11(d) illustrates the MMC’s grid current iga, igb, and igc under RLEL-PLOC. Figure 11(e) represents the iau, ibu, and icu of MMCs under the literature 23’s method. Figure 11(f) represents MMC’s grid current iga, igb, and igc of the under literature 23’s method. Figure 11(g) represents the iau, ibu, and icu of MMCs under the literature 22’s method. Figure 11(h) represents MMC’s grid current iga, igb, and igc of the under literature 22’s method. Figure 11(i) represents the power loss of the T1, D1, T2, D2, and Ploss of the MMC’s SM with the CCSC method, with the RLEL-PLOC method, with the literature 23’s method, and with the literature 22’s method, respectively. It could be noticed that compared with the CCSC method, the maximum power loss of T1 of the RLEL-PLOC method is reduced by 5.4% from 2828 W to 2675 W, and Ploss is reduced by 4.2% from 5541 W to 5310 W. It also could be noticed that compared with the RLEL-PLOC method, although the maximum power loss of T1 of the literature 23’s method is reduced by 2.8% from 2675W to 2601W, Ploss is increased by 4.7% from 5310 W to 5561 W. Compared with the RLEL-PLOC method, although Ploss of the literature 22’s method is reduced by 1.7% from 5310 W to 5221 W, the maximum power loss of T1 of the literature 22’s method is increased by 2% from 2675 W to 2729 W.

4.3. Analysis of Behavior about Capacitor Voltage Ripples

The SM’s capacitor capacitance has a significant influence on the operation, size, and cost for MMCs. The capacitance of SM will decrease along with the decrease of the capacitor voltage ripple. Therefore, the capacitance voltage ripple index is crucial for MMC systems [26]. The capacitor voltage ripple Vrip could be estimated bywhere is the SM capacitor voltage’s peak value and is the SM capacitor voltage’s valley value.

Figure 12 displays the SM’s capacitor voltage ripples in different angle φ under two dominant techniques comprising CCSC and in proposed RLEL-PLOC which could be deduced from the (18) and simulation study system in Section 4. It could be noticed that the RLEL-PLOC has lower capacitor voltage ripples under most operating conditions, which can improve the economy and portability of the MMC.

4.4. Discussion of the Simulation Results

According to the simulation results, it could be obtained that compared with CCSC, the proposed RLEL-PLOC method could decrease both the total power loss and the maximum power loss of the semiconductor devices in the SM. Compared with the RLEL-PLOC method, other methods cannot reduce the total power loss and the maximum power loss of the semiconductor devices in the SM at the same time. Furthermore, the increased loss percentage is high, which will have an adverse impact on the economics or the lifetime of the MMC.

5. Experimental Verification

Figure 13 illustrates the experimental platform photo which was constructed in the lab to validate the put-forward RLEL-PLOC for the MMC. The MMC’s dc bus is made up of a DC voltage source and a resistive load, which are connected in parallel. The SM uses Infineon’s module FF75R12YT30 as the power device. The particular experimental equipment arguments are displayed in Table 5.

5.1. Analysis of Experimental Waveforms

Figure 14 displays the behavior of the MMC running at rated conditions in four control techniques including with the CCSC method, with the RLEL-PLOC method, with the literature 23’s method, and with the literature 22’s method. Figure 14(a) displays the MMC’s iau, ibu, icu, and ibo with the CCSC method, where ibo is the B-phase’s output current of the MMC. Figure 14(b) displays the MMC’s iau, ibu, icu, and ibo with the RLEL-PLOC method. Figure 14(c) displays the MMC’s iau, ibu, icu, and ibo with the literature 23’s method. Figure 14(d) displays the MMC’s iau, ibu, icu, and ibo with the literature 22’s method. Figure 14(e) represents the power loss of the T1, D1, T2, D2, and Ploss of the MMC’s SM with the CCSC method, with the RLEL-PLOC method, with the literature 23’s method, and with the literature 22’s method, respectively. It could be noticed that compared with the CCSC method, the maximum power loss of T2 of the RLEL-PLOC method is reduced by 1.1% from 2.74 W to 2.71 W, and Ploss is reduced by 1.7% from 5.15 W to 5.06 W. It also could be noticed that compared with the RLEL-PLOC method, although the maximum power loss of T2 with the literature 23’s method is reduced by 1.5% from 2.71 W to 2.67 W, Ploss is increased by 3% from 5.06 W to 5.21 W. Compared with the RLEL-PLOC method, although Ploss of the literature 22’s method is reduced by 0.6% from 5.06 W to 5.03 W, the maximum power loss of T2 with the literature 22’s method is increased by 7.4% from 2.71 W to 2.91 W. Hence, the put-forward RLEL-PLOC has an obvious advantage among the existing methods.

5.2. Discussion of the Experimental Results

According to the experimental results, it could be deduced that the proposed RLEL-PLOC method could decrease both the total power loss and the maximum power loss of the semiconductor power devices in the SM compared with CCSC. Compared with the RLEL-PLOC method, other methods cannot reduce the total power loss and the maximum power loss of the semiconductor power devices in the SM at the same time. Moreover, the increased loss percentage is high, which will have an adverse effect on the economics or the lifetime of the MMC.

6. Conclusion

This manuscript proposes an RLEL-PLOC by inpouring the first-best second harmonic circulation current into the arm of the MMC to optimize SM’s power consumption. Compared with the CCSC, the proposed RLEL-PLOC can simultaneously achieve total power loss optimization and maximal power loss optimization in the arm’s SM. Furthermore, the operation cost caused by power loss could be reduced, and the lifetime of the MMC could be improved. Besides, the capacitor voltage ripples under most operation circumstances could be reduced by the proposed RLEL-PLOC. The research results prove the availability of the put-forward RLEL-PLOC for the MMC.

Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

Disclosure

We confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. We wish to submit a new manuscript entitled “Optimized Control for MMCs with Reduced Power Loss and Extended Lifetime” for consideration by the Journal of International Transactions on Electrical Energy Systems.

Conflicts of Interest

The authors declare no conflicts of interest.

Acknowledgments

This study was supported by the Open Foundation of State Key Laboratory of High-End Compressor and System Technology (SKL-YSJ202209), the National Natural Science Foundation of China (52377034, 52177027), the Key Project of Excellent Young Talents in University of Anhui Province (gxyqZD2021090), and the Excellent Youth Project of Natural Science Foundation of Anhui Province (2108085Y18).