Modeling a Heterogeneous Embedded System in Coloured Petri Nets

Algorithm 2

VHDL code on the FPGA system.

process (reset, clk, current_state,

      mf_flag, mf_data)

  begin

    if reset = ‘1’  then

      current_state <= start;

    elsif clk’event and clk = ‘1’  then

      if mf_flag = ‘1’  then

        target_node <= mf_data;

      current_state <= next_state;

      end if;

    end if;

end process;