Revisiting Sum of Residues Modular Multiplication

Table 2

Target FPGA	Virtex2 XC2V1000 with a −6 speed grade, 1M gates, 5120 slices and embedded 18×18 multipliers
Xilinx 6.1i	XST-synthesis
	ISE-place and route
Optimization goal	Speed
Language	VHDL