Journals
Publish with us
Publishing partnerships
About us
Blog
Journal of Electrical and Computer Engineering
Journal overview
For authors
For reviewers
For editors
Table of Contents
Special Issues
Journal of Electrical and Computer Engineering
/
2011
/
Article
/
Fig 8
/
Research Article
Semidigital PLL Design for Low-Cost Low-Power Clock Generation
Figure 8
SDPLL block diagram.