Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Table 1

ADPLL versus conventional PLL.

	ADPLL	Conventional PLL
Power	Fair (depends on tech)	Good
Reconfigurability	Good	Poor
Scalability	Good	Poor
ILeak Immunity	Good	Poor
Linear BW control	Fair	Good
Design complexity	High	Fair
Tech. dependency	High	Fair