Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links
Figure 22
Jitter tolerance for varying clock-to-data skew (a) at 200 ps (b) 500 ps (c) 1 ns. Performance shown for DLL without any compensation techniques, ILO with varying from 0.312 to 0.026, and PLL with BW varied from a maximum of 150 MHz to 65 MHz.
