Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Table 7

Results for the 14T full adder.

Optimal-mode	Symmetric 𝑉bbn = −0.2 V	Asymmetric 𝑉bbn = 0 V
𝐼OFF (pA)	38.47	5.85
𝑡P (ps)	24.03	28.52
Static Power * delay (zJ)	1.10	0.20