Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Table 8

Results for the TG full adder.

Optimal mode	Symmetric; 𝑉bbn = −0.2 V	Asymmetric; 𝑉bbn = 0 V
𝐼OFF (pA)	74.79	11.56
𝑡P (ps)	26.56	24.79
Static power * delay (zJ)	2.38	0.34