Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 9
Results for the PTL full adder.
| | Optimal mode | Symmetric
= 1.4 V | Asymmetric
= 1.2 V |
| | (pA) | 196.35 | 11.42 | | (ps) | 22.50 | 27.19 | | Static power * delay (zJ) | 5.30 | 0.37 |
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