Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Rao, M. V. Nageswara; Hema, Mamidipaka; Raghutu, Ramakrishna; Nuvvula, Ramakrishna S. S.; Kumar, Polamarasetty P.; Colak, Ilhami; Khan, Baseem

doi:https://doi.org/10.1155/2023/7069746

Journal of Electrical and Computer Engineering

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Abstract Introduction Related Works Materials and Methods Results and Discussion Conclusion Data Availability Conflicts of Interest References Copyright Related Articles

Research Article | Open Access

Volume 2023 | Article ID 7069746 | https://doi.org/10.1155/2023/7069746

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

M. V. Nageswara Rao,¹Mamidipaka Hema,²Ramakrishna Raghutu,³Ramakrishna S. S. Nuvvula,³Polamarasetty P. Kumar,³Ilhami Colak,⁴and Baseem Khan⁵

Academic Editor: Suman Lata Tripathi

Received12 Nov 2022

Revised06 May 2023

Accepted26 May 2023

Published07 Jun 2023

Abstract

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (I_leakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), I_leakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of I_leakage.

1. Introduction

Memory cells were designed using complementary metal oxide semiconductor (CMOS), but at lower technology nodes. CMOS suffered from a number of drawbacks, such as subthreshold leakage current (I_leakage) and gate-induced barrier lowering (GIBL), whereas FinFET technology is capable of solving these issues [1]. Bulk CMOS devices are limited to short channel widths of the less than 45 nm, whereas FinFETs can use technology knots as small as 7 nm without sacrificing conducting capabilities. Since the majority of devices are developed in nano range, memory design must utilize the same [2]. Additionally, FinFETs replace MOSFETs, to overcome all drawbacks [3]. Memory cell’s read-out path, threshold voltage and stacking scheme can reduce I_leakage for error-free read operation [4]. The structure comparison of FinFET and normal FET is illustrated in Figure 1.

FinFET technology adds a second gate opposite the normal gate to improve controllability for low voltage operations. FinFET requires both gates to function [5]. When these gates attain equal potential, it reaches shorted gate (SG) mode. Three terminal devices with shorted gates are known as SG FinFETs, whereas 4 terminal devices with physical isolation between gates are known as independent-gate (IG) FinFETs. IG FinFET has a greater degree of flexibility than SG FinFET. Two-dimensional view of FinFETs is depicted in Figure 2.

(a)

(b)

IG operation starts when two gates have dissimilar voltages and the remaining gate is employed to switch devices and control transistor threshold voltage [6–8]. The various height elements of a fin are quantized width (W) and H_fin [9, 10]. The quantization width of a SG FinFET and quantization width of IG FinFET can be calculated using the following equation:

When calculating quantization width IG FinFETs, the fin thickness (T_si) can be ignored. The number of fins is raised in both circumstances to enhance the device’s width. The FinFET structure is discussed in this study from the device to the architecture level, as illustrated in Figure 3.

(a)

(b)

The objective of this research is to develop a 10T SRAM cell using FinFET technology and improve the performance parameters. The power delay product (PDP) need to be reduced to improve the performance and faster response in SRAM. The SNM values for read and hold operations need to be improved. The value of I_leakage must be reduced to provide precise switching capabilities. This research ought to explore the effect of FinFET in the design and development of SRAM cells. The advantages of FinFET are explored to provide a better 10T SRAM cell with 16 nm technology. The improvement in features enables these cells to utilize in real-time applications. The proposed cell’s performance parameters are shown together with their impressions of process parameter modifications, and they are contrasted with previously proposed SRAM cells.

The solution for SRAM cell stability issue may be classified into two ways. First one is circuit topologies, and the second is the use of nonconventional MOSFETs. In a 7T SRAM, Akashe and Sharma [11] demonstrated that lowering the power supply lowers gate I_leakage. The voltage at ground was then increased using the power gating technique, which lowered gate I_leakage as well. Finally, effective voltages between the two terminals were adjusted, resulting in a considerable drop in both I_leakage. The double-feedback 8T SRAM cell described by Vaknim et al. [12] decreases leakage power. In this research, the authors used a power gating technique on a typical 6T SRAM cell, in which the supply voltage is dropped in standby mode by severing the link from the power supply to the cell and also boosting the ground potential to avoid providing a direct path to ground. As a result, the leakage power has decreased. Moradi et al. [13] suggested a new SRAM design that uses body biassing to lower the power supply to 0.3 V, which is extremely low for proper SRAM cell operation.

Zhang et al. [14] looked at three different types of I_leakage in bit cells. Leakage reduction strategies such as device body biassing, source biassing with controls, dynamic supply voltage, negative word line voltage, and bit line floating structures were also examined. Ensan et al. [15] designed a single-ended strong 11T cell that is based on feedback-oriented FinFET. Dynamic power reduction occurs because the SRAM cell has single bit interconnection for write and read operations. By using segregated paths and feedback-assisted techniques, respectively, this cell can enhance write SNM (WSNM) and read SNM (RSNM). These enhancements slow down reading and writing speed. It is discovered as reliable close to the threshold. Ahmad et al. [16] proposed cells that use 11T to enhance RSNM and WSNM while lowering power consumption. The configuration, which was created in accordance with 45 nm technological standards, has a 2x larger surface area than a 6T cells.

Sachdeva and Tomar [17] discussed 12T cell that utilize differential writing and one end reading architectures. Even though it uses the power gating write-assist mechanism, read disturbance still affects it and nevertheless displays significant WSNM. This cell, however, is adversely affected by the space and decrease the dynamic read power consumption. According to Nidhi et al. [18], two access transistors and two straightforward cross-coupled inverters are often found in SRAM cells. The access transistors that connect Bit Line (BL) are switched ON to enable operations. Medium consumption of power and reduced I_leakage are the most significant benefits. Lakshmi et al. [19] introduced 8T FinFET SRAM cell to get around the shortcomings of the 6T cell. Low stationary noise margin (SNM) in read mode may exhibit better writing capabilities. As a result, circuit designers have more freedom to optimise and the functions are perfectly isolated.

Yatimi et al. [20] created a 9T cell with double subsection as its main component. Data are kept in the primary subsection. The data kept in the cell affects how transistors (XM8 and XM7) function. XM9 is dependent upon the distinct read signal (RD). Write access is carried out by the write access transistors under the control of WBL and WBLB. Additionally, the read access transistor carries out read access that is managed by RWL. 10T SRAM cell developed by Singh et al. [21] has two access transistors. Transistors in the read path are used to implement the dual threshold-voltage approach, which improves the current ON or else OFF ratio. RWL is connected to both the source and gate of the XM10 and XM9 transistors. Additionally, access FinFETs are connected to WWL, BL, and BLB. The transistors XM7 and XM8 increase the write margin. This research attempts to overcome these technical gaps through our effort in developing a better SRAM cell for future low-power applications. Low power memory circuit design and fault modelling have also been considered in the review.

Shruti Oza [22] conducted study on SRAM technology provides high performance and low power consumption. To reduce short channel effects (SCE) and leakage current in deep-submicron circuits, FinFET has emerged as an alternative to bulk FETs. Its favorable device characteristics make it suitable for nanoscale memory circuits design, especially with the increasing impact of process variations in ultra-deep-submicron technologies. FinFETs are becoming more popular in industry due to their efficiency.

Chakraborty et al. [23] conducted a study on optimizing performance parameters such as power, delay, leakage, and time to market has been a key focus of the IC industry since its inception. Efforts have been increasing over time to achieve the maximum throughput from these settings, particularly with regards to the voltage of the power source. This is the driving force behind Moore’s Law.

Pal et al. [24] conducted a study on a comparison of the proposed design to contemporary SRAM designs, including 7T feedback-cutting, FD8T and SEDF9T bitcells, has evaluated design metrics and reliability under process variations. Minimized dynamic and leakage power are achieved due to single bitline and transistor stacking in the discharge path, respectively

In the study by Jiang et al. [25], there have been few studies comparing the state-of-the-art soft error tolerant SRAM cells in near/subthreshold voltage regarding write stability, read/write access time, and RSNM under temperature and process corner variations. Existing reports mainly focus on conventional soft error vulnerable SRAM cells.

Xue et al. [26] found that memory in computers is used to store information and instructions. It can be temporary or permanent. Contrasting serial access memory is random access memory (RAM), which allows immediate access for reading and writing. Technological advancements enable complex designs on a single chip, having small size, low power consumption, cheap cost, and high speed.

Navaneetha and Bikshalu [27] state that the VLSI industry requires anticipating tolerance of variability to ensure optimized performance of FinFET circuits. In this research, the Cadence Virtuoso tool is used to investigate the impact of fluctuations in voltage and temperature on 7 nm FinFET-based circuits.

In the study by Ahmed et al. [28], soft errors in semiconductor memories can be caused by charged particles striking sensitive nodes. Voltage and technology scaling has drastically increased the vulnerability of SRAMs to soft errors. Table 1 presents the existing characteristics P-type FinFETsof finfet. Table 2 presents the performance and reliability of 6T and 8T AUF SRAM.

3. Materials and Methods

The proposed methodology emphasises in developing less power consuming FinFET-oriented SRAM cells that outperform conventional 6T SRAM cells. A 10T SRAM cell based on a MOSFET is defined, as illustrated in Figure 4. Since read and write word lines are shared, a distinct path for read operation having 4 transistors is created to increase read SNM while maintaining write SNM [31].

Read current (I_on or I_read) is identified to be the summation of current passing through the drains of transistors N1 (I_Dn) as well as P1 (I_Dp) throughout the read process. The size limitations of transistor N3, N5, and N8 have a significant impact on I_ON in the proposed 10T topology [32]. To evaluate this model for I_read, the drain in N3 and N4 must be articulated. The drain current can be analysed as follows:where η denotes the swing, V_T is the thermal voltage, and I₀ denotes drain current given by

To keep SNM in the 10T SRAM cell, RSNM is drawn approximately equal. Due to bit line (BL) capacitances, this circuit runs at ultra-low supply voltages [33]. BLs are connected to access transistors, while word lines are frequently connected to BL, BLB, and both transistors (WL). Individual transistors for read access and write pass are used to improve SNM and stability. Read access transistors M7–M9 are utilized, while write access transistors M6, M5 are used. Different access transistors enable transistors to be sized for better read and write stability. I_leakage and sneaky current were present in prior SRAM cells, comparable to normal SRAM cells, resulting in read errors [34]. Three transistors are employed in read cycle of this 10T SRAM cell, which employs stacking techniques and improves the I_ON/I_OFF ratio. Figure 5 depicts the suggested circuit with FinFET for an ultra-low-power SRAM cell.

Since read transistors are not shared with other cells, I_leakage does not occur in the path of read operation. As a result, having a higher I_ON/I_OFF ratio allows more SRAM cells to share the same bit line. Because of the greater I_ON/I_OFF ratio, the SRAM peripheral for read and write of each column can be shared by more and more cells [35]. The more space, power, and money saved in the design of SRAM for huge storing capacity, the better. The read word line (RWL) is connected to M9 and M8. Word line (WL) is connected to M5, M3, and M1, hence read and write margins have been increased. Reduce static current even further by using access transistors that are twice the size of pull-up transistors. This cell comprises of 3 operating modes, which are further discussed: read, write, and hold [36]. Using access transistors that are twice the size of pull-up transistors to further reduce static current there will be data to be stored on both bit lines. Data are not sent to QB and Q until WWL is enabled. RWL is constantly OFF in write mode. To improve write stability, M10 transistors will supply virtual GND [37]. When the potential of the WWL is low, BLB and BL are detached from SRAM. Since RWL is at a low potential there is an increment in threshold voltage [38]. In the hold state, power consumption and I_leakage are reduced, which is advantageous. M10 increases the margin in write operation and decrease static current by strengthening draw-up and pull-down networks.

One of the crucial factors in memory design that determines its intended use is power dissipation, which should be kept to a minimum for bio-medical applications. The following equation can be used to illustrate how a FinFET reduces power usage.

Supply voltage is VDD; low-to-high propagation delay TpLH, high-to-low propagation delay TpHL, propagation delay Tp, static power dissipation Ps, dynamic power dissipation PD, power dissipation when short-circuited PSC, and power delay product PDP are all included in the analysis.

4. Results and Discussion

During the initial phase (0–20 ns) of the spice simulator, WL = 1, delivered data on BLs towards QB and Q are provided by M5 and M6. WL is set to logic “1” for write operation. The 2^nd stage (20−40 ns) denotes a hold operation for WL = 0. This will keep access to be OFF and delivered data on BLs will not reflect on the node of a cell. WL is activated during third phase (40 to 60 ns), and the data on the BL = “0” (for initial 20 ns) and BL = “1” (for remaining 20 ns). Since the data available in BLB is complementary, data on node Q will change in the same way. Half of the V_DD is precharged with RBL. While QB is at logic “1,” M7 is ON, and when RWL is at logic “1,” M8, M9 is ON. As a result, the precharged read BL is cleared by incrementing the BL discharge current. As a result, I_read rises, time requirement falls. Table 3 displays the outcomes from the investigation of numerous parameters used in the design of FinFET-oriented SRAM cells at 16 nm.

The SRAM cell size for 10T and 6T with 16 nm is given in Tables 4 and 5. The fin number of FinFET is listed in Table 2. The measurement of FinFET is displayed in Table 5, and the length of all transistors is the same, i.e., 16 nm.

Figure 6 shows how simulation is performed for 200 ns depending on the voltages provided. During the read operation, RWL is at logic “1”, as illustrated in Figure 7. QB = “0” for the 1^st stage (0–50 ns), and QB = “1” for next stage (50−200 ns).

The performance parameters considered in this work are power, delay, and power delay product (PDP). PDP is calculated by multiplying average power wasted during the delay in propagation. PDP is calculated theoretically using SRAM cell transient analysis. The suggested SRAM cells have the lowest PDP (for write and read), as displayed in Tables 6 and 7. These tables show that the proposed 10T SRAM cell has a lower PDP compared to 6T cell. Figure 8 presents the performance of the proposed SRAM cells in write mode.

Figure 9 presents the performance of the proposed SRAM cells in read mode. Subthreshold current flows in through transistors with no applied input, nevertheless some current is employed. I_leakage is kept in hold if WL has 0 V. Table 8 compares the I_leakage of different SRAM cells.

Figure 10 presents the I_leakage Analysis of SRAM cells. SNM is considered to be the smallest voltage (noise) required to alter the hold data in an SRAM cell and is used to describe the cell’s stability. SNM is calculated by performing separate DC analyses on 2 inverters. SNM is calculated using a graph that identifies the largest square fit inside a butterfly curve, when the inverters are connected in cascade. The calculated values from SRAM cell butterfly curves are shown in Table 9.

The SNM of 6T version and 10T version are measured in the read and hold states. A significant disadvantage of a 6T topology is high RSNM. Figure 11 depicts the butterfly curves of SNM of 6T and 10T topologies in hold and read operations.

(a)

(b)

(c)

(d)

The performance of the proposed 10T SRAM cell based on FinFET is analysed with respect to traditional MOSFET-based 6T and 10T SRAM cells. While considering PDP in write mode, FinFET shows higher level of improvement (68.58% for 6T and 80.80% for 10T). While considering the PDP in read mode, FinFET shows improvement (40.01% for 6T and 50.65% for 10T). This indicates that the proposed 10T SRAM cells based on FinFET consumes less power and the time delay during operations is very low. During the evaluation of I_leakage, FinFET shows a higher level of improvement (50.22% for 6T and 25.53% for 10T). This indicates that I_leakage in proposed 10T SRAM cells based on FinFET is very low compared to MOSFET-based SRAM cells. For 6 T SRAM cells, there is an improvement of 13.63% in HSNM and 15.38% in RSNM for FinFET. For 10T SRAM cells, there is an improvement of 22.20% in HSNM and 22.20% in RSNM for FinFET. This indicates that SNM for proposed 10T SRAM cells based on FinFET is large while comparing MOSFET-based SRAM. The minimum data retention voltage (DRV) of the proposed SRAM cell is 68 mV.

The performance of the proposed 10T FinFET SRAM cell is compared with state-of the art models such as 7T, TA8T, 9T, PPN10 T, and D2p11T. The PDP of the proposed model is compared with other models, as illustrated in Figure 12.

The PDP of the proposed model is lowest for read operation as well as write operation. TA8T exhibits the maximum PDP of 3.4 nJ in read operation. The proposed model provides 55.85% less PDP than the TA8T method. The second lowest value of 2.17 nJ is provided by PPN10T method which is 30% higher than proposed scheme. The 7T method exhibits the maximum PDP of 1310 nJ in write operation. The proposed model provides 54.04% less PDP than the 7T method. The second lowest value 667 nJ is provided by the TA8T method which is 9.7% higher than proposed scheme. The SNM of the proposed model is compared with other models, as illustrated in Figure 13.

The SNM of the proposed model is highest for read operation as well as hold operation. The proposed scheme exhibits the maximum value of 270 mV for both HSNM and RSNM. The proposed model provides 22 mV more in the case of RSNM and 60 mV more in the case of HSNM when compared to the 7T scheme. The I_leakage of the proposed model is compared with other models, as illustrated in Figure 14.

The I_leakage of proposed model is 29.439 mA, which is the lowest compared to other methods. The proposed model provides 25.404 mA less than the PPN10T scheme. This indicates that the proposed 10T circuit offers high read stability, low power consumption, and excellent performance. Any innovative topology used to limit read or write PDP while preserving stability may result in a trade-off of increased bitcell access time. The 10T SRAM structure offers several advantages over 6T SRAM, such as improved bitcell stability and a shorter access time. However, it also requires more transistors than the 6T SRAM structure in order to provide these benefits, which can lead to a decrease in the SRAM circuit’s density within the CPU. This increased number of transistors can reduce the overall efficiency of the CPU, as the larger area requirement restricts the amount of space available on the chip. Furthermore, the additional areas needed for fabrication can limit the efficiency of the CPU due to the increased overhead. In summary, 10T SRAM provides better bitcell stability, reduced access time, and improved read/write capabilities compared to 6T SRAM, but at the cost of decreased SRAM circuit density inside the CPU and greater fabrication costs. Thus, when considering the advantages and disadvantages of both 10T and 6T SRAM structures, designers must carefully evaluate the tradeoff between features and SRAM density before deciding which to use.

5. Conclusion

This paper recommends the usage of a 10T SRAM cell incorporating FinFET for ultra-low dissipation in power along with read and write stability. The developed architecture based on FinFET must run at a higher range of frequencies because of the large I_D and safer operation in the zone of subthreshold. The proposed SRAM cell reduced the PDP and I_leakage. It improved stability of read operation while comparing with 6T counterpart. This cell is designed with FinFETs at 16 nm technology knot. Various SRAM cells with ultra-low power applications can be created as a result of this research. In contrast with 6T SRAM cell and earlier low power SRAM cells, the proposed cell exhibits significant SNM along with high-speed access. Because of high I_D requirements and its effective operations throughout the region of subthreshold, the characteristic of developed design must function at high frequency. This design can further be utilized to build memory elements as small as 32 nm without the short channel effects (SCE) that affect CMOS technology. In comparison to MOSEFET models, the proposed 10T SRAM based on FinFET offers PDP reductions of 80.80% in write mode and 50.65% in read mode. Both SNM and I_leakage have improved by 22.20% and 25.53%, respectively. Future work based on the development of the 10T SRAM cell incorporating FinFET could focus on applying this technology in other ultra-low power applications. Additionally, further research could explore potential use cases of the 10T SRAM cell in the construction of larger memory components such as caches and memories. The area efficiency of the proposed 10T SRAM based on FinFET is higher than that of traditional 6T SRAM and other low-power SRAM cells. Compared to MOSEFET models, it provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode.

Data Availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

References

J. V. Suman, K. K. Cheepurupalli, and H. L. Allasi, “Design of polymer-based trigate nanoscale FinFET for the implementation of two-stage operational amplifier,” International Journal of Polymer Science, vol. 2022, Article ID 3963188, 12 pages, 2022.
View at: Publisher Site | Google Scholar
L. Xue, B. Wu, B. Zhang et al., “An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs,” IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 3, pp. 484–495, 2018.
View at: Publisher Site | Google Scholar
H. Amrouch, G. Pahwa, A. D. Gaidhane et al., “Impact of variability on processor performance in negative capacitance finfet technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3127–3137, 2020.
View at: Publisher Site | Google Scholar
M. A. Turi and J. G. Delgado-Frias, “Effective low leakage 6T and 8T FinFET SRAMs: using cells with reverse-biased FinFETs, near-threshold operation, and power gating,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 765–769, 2020.
View at: Publisher Site | Google Scholar
S. Kaushal and A. K. Rana, “Negative capacitance junctionless FinFET for low power applications: an innovative approach,” Silicon, vol. 14, pp. 6719–6728, 2022.
View at: Publisher Site | Google Scholar
M. S. Badran, H. H. Issa, S. M. Eisa, and H. F. Ragai, “Low leakage current symmetrical Dual-k 7 nm trigate bulk underlap FinFET for ultra low power applications,” IEEE Access, vol. 7, pp. 17256–17262, 2019.
View at: Publisher Site | Google Scholar
K. Subannan Palanisamy and R. Ramachandran, “FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic,” International Journal of Circuit Theory and Applications, vol. 48, no. 8, pp. 1304–1318, 2020.
View at: Publisher Site | Google Scholar
S. Sayyah Ensan, M. H. Moaiyeri, B. Ebrahimi, S. Hessabi, and A. Afzali-Kusha, “A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology,” Journal of Computational Electronics, vol. 18, no. 2, pp. 519–526, 2019.
View at: Publisher Site | Google Scholar
T. S. Kumar and S. L. Tripathi, “Leakage reduction in 18 nm FinFET based 7T SRAM Cell using self-controllable voltage level technique,” Wireless Personal Communications, vol. 116, no. 3, pp. 1837–1847, 2021.
View at: Publisher Site | Google Scholar
C. Duari, S. Birla, and A. K. Singh, “Dual port 8T SRAM cell using FinFET & CMOS logic for leakage reduction and enhanced read & write stability,” Journal of Integrated Circuits and Systems, vol. 15, no. 2, pp. 1–7, 2020.
View at: Publisher Site | Google Scholar
S. Akashe and S. Sharma, “Leakage current reduction techniques for 7T SRAM cell in 45 nm technology,” Wireless Personal Communications, vol. 71, no. 1, pp. 123–136, 2013.
View at: Publisher Site | Google Scholar
A. Vaknin, O. Yona, and A. Teman, “A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation,” in Proceedings of the 2013 IEEE SOI-3d-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2, IEEE, Monterey, CA, USA, October 2013.
View at: Google Scholar
F. Moradi, S. K. Gupta, G. Panagopoulos, D. T. Wisland, H. Mahmoodi, and K. Roy, “Asymmetrically doped FinFETs for low-power robust SRAMs,” IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4241–4249, 2011.
View at: Publisher Site | Google Scholar
L. J. Zhang, C. Wu, Y. Q. Ma, J. B. Zheng, and L. F. Mao, “Leakage power reduction techniques of 55 nm SRAM cells,” IETE Technical Review, vol. 28, no. 2, pp. 135–145, 2011.
View at: Publisher Site | Google Scholar
S. S. Ensan, M. H. Moaiyeri, and S. Hessabi, “A robust and low-power near-threshold SRAM in 10-nm FinFET technology,” Analog Integrated Circuits and Signal Processing, vol. 94, no. 3, pp. 497–506, 2018.
View at: Publisher Site | Google Scholar
S. Ahmad, M. K. Gupta, N. Alam, and M. Hasan, “Single-ended Schmitt-trigger-based robust low-power SRAM cell,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 8, pp. 2634–2642, 2016.
View at: Publisher Site | Google Scholar
A. Sachdeva and V. K. Tomar, “A Schmitt-trigger based low read power 12T SRAM cell,” Analog Integrated Circuits and Signal Processing, vol. 105, no. 2, pp. 275–295, 2020.
View at: Publisher Site | Google Scholar
T. Nidhi, N. Vaibhav, J. R. Kamal, and C. S. Yogesh, “Performance parameters of low power SRAM cells: a review,” i-manager's Journal on Circuits and Systems, vol. 6, no. 1, p. 25, 2018.
View at: Publisher Site | Google Scholar
T. V. Lakshmi and M. Kamaraju, “A review on SRAM memory design using FinFET technology,” International Journal of System Dynamics Applications, vol. 11, pp. 1–21, 2021.
View at: Google Scholar
H. Yatimi and E. Aroudam, “Standalone photovoltaic system with maximum power point tracking: modeling and simulation,” International Journal of System Dynamics Applications, vol. 7, no. 3, pp. 94–111, 2018.
View at: Publisher Site | Google Scholar
A. Singh, Y. Sharma, A. Sharma, and A. Pandey, “A novel 20nm FinFET based 10T SRAM cell design for improved performance,” in International Symposium on VLSI Design and Test, pp. 523–531, Springer, Singapore, 2019.
View at: Google Scholar
S. Oza, “FinFET based SRAM design for low power applications finfet based SRAM design for low power APPLICATIONS,2,” International Journal of Electrical Electronics and Data Communication, vol. 03, pp. 2320–2084, 2014.
View at: Google Scholar
A. Chakraborty, R. Singh Tomar, and M. Sharma, “Optimization of low power 12 T SRAM bit cell using FinFET in 32 nm technology,” Materials Today: Proceedings, vol. 80, pp. 226–232, 2023.
View at: Publisher Site | Google Scholar
S. Pal, S. Bose, K. Wing-Hung, and A. Islam, “A highly stable reliable SRAM cell design for low power applications,” Microelectronics Reliability, vol. 105, Article ID 113503, 2020.
View at: Google Scholar
J. Jiang, Y. Xu, W. Zhu, J. Xiao, and S. Zou, “Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 967–977, 2019.
View at: Publisher Site | Google Scholar
X. Xue, A. Sai Kumar, O. I. Khalaf et al., “Design and performance analysis of 32 × 32 memory array SRAM for low-power applications,” Electronics, vol. 12, no. 4, p. 834, 2023.
View at: Publisher Site | Google Scholar
A. Navaneetha and K. Bikshalu, “Reliability analysis of FinFET based high performance circuits,” Electronics, vol. 12, no. 6, p. 1407, 2023.
View at: Publisher Site | Google Scholar
I. Alouani, W. M. Elsharkasy, A. M. Eltawil, F. J. Kurdahi, S. Niar, and F. Kurdahi, “AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement,” IET Circuits, Devices and Systems, vol. 11, no. 1, pp. 89–94, 2017.
View at: Publisher Site | Google Scholar
mospace, “Static random-access memory designs based on different finfets,” 2019, https://mospace.umsystem.edu/xmlui/bitstream/handle/10355/71051/Nizam_umkc_0134P_11518.pdf?isAllowed=y&sequence=1.
View at: Google Scholar
M. U. Mohammed, A. Nizam, L. Ali, and M. H. Chowdhury, “FinFET based SRAMs in Sub-10nm domain,” Microelectronics Journal, vol. 114, Article ID 105116, 2021.
View at: Publisher Site | Google Scholar
S. Saxena and R. Mehra, “Low‐power and high‐speed 13T SRAM cell using FinFETs,” IET Circuits, Devices and Systems, vol. 11, no. 3, pp. 250–255, 2017.
View at: Publisher Site | Google Scholar
B. Zeinali, J. K. Madsen, P. Raghavan, and F. Moradi, “Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology,” International Journal of Circuit Theory and Applications, vol. 45, no. 11, pp. 1647–1659, 2017.
View at: Publisher Site | Google Scholar
A. Calimera, A. Macii, E. Macii, and M. Poncino, “Design techniques and architectures for low-leakage SRAMs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1992–2007, 2012.
View at: Publisher Site | Google Scholar
H. Farkhani, A. Peiravi, J. M. Kargaard, and F. Moradi, “Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective,” in Proceedings of the 2014 27th IEEE International System-On-Chip Conference (SOCC), pp. 449–454, IEEE, Las Vegas, NV, USA, September 2014.
View at: Google Scholar
G. Pasandi and S. M. Fakhraie, “An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs,” IEEE Transactions on Electron Devices, vol. 61, no. 7, pp. 2357–2363, 2014.
View at: Publisher Site | Google Scholar
D. Bhattacharya and N. K. Jha, “Ultra-high density monolithic 3-D FinFET SRAM with enhanced read stability,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 8, pp. 1176–1187, 2016.
View at: Publisher Site | Google Scholar
T. Dutta, G. Pahwa, A. R. Trivedi, S. Sinha, A. Agarwal, and Y. S. Chauhan, “Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1161–1164, 2017.
View at: Publisher Site | Google Scholar
B. Raj, A. K. Saxena, and S. Dasgupta, “Nanoscale FinFET based SRAM cell design: analysis of performance metric, process variation, underlapped FinFET, and temperature effect,” IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38–50, 2011.
View at: Publisher Site | Google Scholar

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Copyright © 2023 M. V. Nageswara Rao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Journal of Electrical and Computer Engineering

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Abstract

1. Introduction

2. Related Works

3. Materials and Methods

4. Results and Discussion

5. Conclusion

Data Availability

Conflicts of Interest

References

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