Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Table 7

Performance of proposed SRAM cells in read mode.

SRAM (T)	Transistor	Power (nW)	Delay (ns)	PDP (nJ)	Percentage improvement
6	MOSFET	31.234	0.27	8.43	40.01
	FinFET	28.321	0.16	4.53
10	MOSFET	16.7	0.1825	3.04	50.65
	FinFET	12.52	0.12	1.50