Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

Dash, Sandeep K.; De, Bishnu Prasad; Samanta, Pravin K.; Appasani, Bhargav; Kar, Rajib; Mandal, Durbadal; Bizon, Nicu

doi:https://doi.org/10.1155/2023/7621594

Journal of Electrical and Computer Engineering

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Research Article | Open Access

Volume 2023 | Article ID 7621594 | https://doi.org/10.1155/2023/7621594

Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

Sandeep K. Dash,¹Bishnu Prasad De,¹Pravin K. Samanta,¹Bhargav Appasani,¹Rajib Kar,²Durbadal Mandal,²and Nicu Bizon^3,4,5

Academic Editor: M. Jamal Deen

Received07 Mar 2023

Revised26 May 2023

Accepted20 Jul 2023

Published08 Aug 2023

Abstract

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

1. Introduction

Circuit sizing is a tedious problem for the IC engineer. Evolutionary techniques are efficient in solving circuit sizing problems. J. H. Holland invented the genetic algorithm (GA) [1]. GA is utilized for op-amp design in [2]. With the help of GA, power dissipation is optimized for an active load differential amplifier [3]. GA-based VLSI circuit partitioning is reported in [4]. The floorplan area is optimized using GA in [5]. A CMOS circuit synthesizer called DARWIN [6] is proposed for op-amp design. Particle swarm optimization (PSO) [7, 8] is a proficient evolutionary method. PSO-based design of op-amp is reported in [9, 10]. PSO is applied for the optimal design of current conveyors [11]. Storn and Price introduced differential evolution (DE) [12]. DE is used for analog circuit synthesis in [13]. DE-based channel routing for the VLSI circuit is proposed in [14]. DE is useful for VLSI floorplanning [15]. A hybrid particle swarm optimization (PSO) method is proposed for the optimization of an operational amplifier [16] and a differential amplifier [17]. In [18], a rule-guided genetic algorithm (RG-GA) is employed to design an operational amplifier. A machine learning-assisted sizing technique [19] is introduced to design amplifiers and a comparator in analog circuits. Bayesian optimization approaches have been reported for analog circuit sizing in [20, 21]. Deep reinforcement learning [22] is utilized for sizing a two-stage operational amplifier. Various evolutionary optimization techniques [23–28] are applied to the circuit sizing of other analog VLSI circuits. Many optimization problems exhibit a multiobjective nature, and evolutionary approaches prove to be beneficial for solving such problems. In 2003, Babu and Jehan introduced the multiobjective differential evolutionary algorithm (MDEA) [29]. The multiobjective DE [30] is employed to address the power dispatch problem, and the PID controller tuning using a multiobjective DE is discussed in [31]. Several studies on multiobjective numerical optimization have been documented in [32–35]. A CMOS voltage reference circuit is proposed in [36, 37], and a nine-stage ring oscillator circuit is designed in [38, 39].

The paper’s contribution is the application of a state-of-the-art algorithm for the optimal design of a voltage reference circuit and a ring oscillator circuit. This article aims to optimize the transistor’s dimensions for each circuit for better performance parameters. The paper is written as follows: the optimization problem for each circuit is formulated in Section 2. MDEA is described in the next section. In Section 4, the simulation results are explained. Section 5 concludes the article.

2. Optimization Problem Formulation

The CMOS voltage reference circuit is shown in Figure 1, and the nine-stage ring oscillator circuit is shown in Figure 2. MDEA is utilized for the optimal design of these two circuits.

2.1. Design of a CMOS Voltage Reference Circuit

For MOSFET, the drain current I_D at the subthreshold region is described aswhere K = W/L, μ denotes the carrier mobility, C_ox denotes the oxide capacitance/area, V_T denotes the thermal voltage, V_TH represents the threshold voltage for MOSFET, and η denotes the subthreshold slope factor.

For large values of V_D, I_D is not dependent on V_DS and is represented by

V_GS1 in M₁ equals the sum of V_GS2 in M₂ and V_DSR1 in M_R1.

The current flowing through transistors M₁ and M₂ is equal to I_P. The value of V_DSR1 is given by

The resistance of the MOS transistor M_R1 is given by

The current I_P is represented as

The current flowing through M₄ and M₆ is 3I_P and 2I_P, respectively. The output reference voltage V_REF is represented as

V_TH and V_T have negative and positive TC, respectively; the V_REF can be obtained with zero TC by setting the transistor’s dimensions.

The design problem is formulated as follows:(1)Preserve the dimension of current mirror transistors MC₁, MC₂ and M₁, M₂.(2)Preserve the dimension of transistors MC₃, MC₄, and MC₅ for matching purpose.(3)The current through MC₃, MC₄, and MC₅ must be greater than the leakage currents, i.e., 1 nA.(4)Preserve the dimension of transistors M₃, M₄, M₅, M₆, and M₇ for matching purpose.(5)The optimization problem aims to reduce the variation for the V_REF within the temperature range from −40°C to 125°C. The variation of V_REF with temperature is represented as where V_max and V_min denote the absolute maximum and minimum of the difference between V_REF and V_Target within the temperature range −40°C to 125°C.(6)The cost function (CF) is formulated as

2.2. Design of the CMOS Ring Oscillator Circuit

The nine-stage RO circuit is shown in Figure 2. The oscillation frequency (f_osc) is defined aswhere η varies between 0.7 and 0.9, N denotes the number of CMOS inverter stages, I_r (t_f) denotes the rise (fall) time, I_D is the drain current, C_tot represents the total capacitance, and V_DD represents the supply.

The total capacitance C_tot is given bywhere L_n (L_p) denotes the length of NMOS (PMOS) and W_n (W_p) represents width of the NMOS (PMOS).

The average power dissipation [40] of the RO is represented as

The phase noise [40] is defined aswhere , δf is the offset frequency, δV denotes the gate over drive voltage, T represents the absolute temperature, and k denotes the Boltzmann constant, γ = 2/3

The figure of merit (FOM) is given as

The optimization problem can be represented as follows: (1) minimization of L{δf}, (2) minimization of the power, and (3) minimize FOM.

The design constraints are given as follows:

The MDEA is applied to get the design parameters for the RO.

3. Multiobjective Differential Evolutionary Algorithm (MDEA)

The multiobjective differential evolution (MODE) algorithm [29–31] is a specialized variant of the differential evolution (DE) algorithm developed to tackle multiobjective optimization problems. By integrating the principles of differential evolution and Pareto dominance, MODE enables the exploration of trade-off solutions that balance conflicting objectives. The following are the key steps involved in the MODE algorithm:(1)Initialization: An initial population of candidate solutions is generated randomly within the search space.(2)Mutation: Each individual in the population undergoes mutation, where a mutant solution is created by perturbing the individual using a mutation operator. The mutation operator typically involves the difference between multiple individuals.(3)Crossover: The mutant solutions are combined with the original individuals to produce trial solutions. The crossover process merges the components of the mutant and original solutions.(4)Selection: The trial solutions are evaluated, and individuals are selected for the next generation based on Pareto dominance. The selection process compares solutions, determining their superiority or noninferiority relative to others in the population. Dominated solutions are eliminated, while nondominated solutions are retained.(5)Termination: Steps 2 to 4 are repeated until a termination criterion is met. This criterion may involve a maximum number of generations, the attainment of a specific convergence level, or other predefined stopping conditions.

The MODE algorithm employs a population-based evolutionary search strategy to explore the solution space and discover diverse solutions that represent trade-offs among multiple objectives. Its objective is to approximate the Pareto-optimal front, which comprises the set of nondominated solutions. The algorithmic steps are described as follows: (see Algorithm 1).

	Step 1: Initialize D (dimension of optimization problem), N_p (population size), F (scaling factor), CR (crossover rate), and _max (Maximum iteration cycle)
	Step 2:Initialize for = 0 the D-dimensional N_p populations as
	(where i = 1, 2,..., N_P) within the bounds and .
	Step 3: for i = 1 to N_p
	{
	for j = 1 to D
	{

	}
	}
	Step 4: for = 1 to
	{
	for i = 1 to N_p
	{

	where
	Compute for each where .
	j_rand = [rand(0,1) x D];
	for j = 1 to D.
	{

	}
	Determine whether the target vector survives for the next generation.

	}
	}

Apply the naïve and slow approach [32] to eliminate the dominant solutions from the previous generation.

Output the nondominated solutions.

4. Simulation Results and Discussions

The MDEA technique is executed in MATLAB for the analog VLSI circuits depicted in Figures 1 and 2, respectively. Table 1 displays the parameters of MDEA. The optimal transistor dimensions for each circuit are obtained from MDEA. Cadence is used to simulate the circuits for authentication purposes. A discussion of the results is given below.

4.1. Simulation Results for the CMOS Voltage Reference Circuit

The constraints for the first circuit are given as 1 μm ≤ L ≤ 20 μm, 0.1 μm ≤ W ≤ 50 μm, VDD = 1.2 V, VREF = 550 mV, and IP = 100 nA. Table 2 shows the optimal transistor sizing obtained from MDEA. The voltage reference circuit is implemented with these design parameters in Cadence Virtuoso. The variation of VREF with the temperature is displayed in Figure 3 at different process corners such as TT, SF, FS, FF, and SS. The deviation of VREF from the target value of 0.55 V is less than 10% across different process corners. The variation of VREF with respect to temperature and supply voltage for the TT process is shown in Figure 4. It is observed that the reference voltage varies from 0.53 V to 0.6 V for the TT process. The variation of VREF with respect to temperature and supply voltage for the SS process is shown in Figure 5. It is observed that the reference voltage varies from 0.54 V to 0.61 V for the SS process. The variation of VREF with respect to temperature and supply voltage for the FF process is shown in Figure 6. It is observed that the reference voltage varies from 0.52 V to 0.59 V for the FF process. The variation of VREF with respect to temperature and supply voltage for the SF process is shown in Figure 7. It is observed that the reference voltage varies from 0.53 V to 0.61 V for the SF process. The variation of VREF with respect to temperature and supply voltage for the FS process is shown in Figure 8. It is observed that the reference voltage varies from 0.53 V to 0.59 V for the FS process. The temperature is varied from −40°C to 125°C, the supply voltage is from 1 V to 1.4 V for all the processes, and the maximum variation of the reference voltage from the target value is less than 12.2%. Table 3 demonstrates the different performance parameters of the voltage reference circuit. The power dissipation of the voltage reference circuit is 600 nW. It is evident from Figures 4–8 and Table 3 that the voltage reference circuit is very robust for variation against temperature, supply voltage, and different process corners. MDEA shows better results as compared to SCA-mGWO [30].

4.2. Simulation Results for the CMOS Ring Oscillator Circuit

Table 4 presents the constraints and optimal design parameters obtained through the application of the multiobjective differential evolutionary algorithm (MDEA). The ring oscillator (RO) circuit is designed using Cadence Virtuoso with the gpdk090 library. The transient response of the RO is illustrated in Figure 9, showcasing oscillation at a frequency of 2.001 GHz. Figure 10 displays the phase noise plot for the designed RO circuit, revealing a phase noise of −87 dBc/Hz at 1 MHz. The power dissipation plot for the RO circuit is shown in Figure 11, with the optimized circuit dissipating a power of 71 μW. The achieved figure of merit (FOM) for this design is −164.487 dBc/Hz. In [38], a nine-stage RO circuit was also investigated, operating at a frequency of 2.13 GHz. At this frequency, the power dissipation was reported as 477.7 μW, and the phase noise was measured as −91.4 dBc/Hz at 1 MHz. The reported FOM in [38] was −16118 dBc/Hz. Comparatively, the MDEA-based design of the RO circuit demonstrates superior performance parameters, as summarized in Table 5.

5. Conclusion

In this study, the multiobjective differential evolutionary algorithm (MDEA) is employed to achieve optimal designs for CMOS VLSI circuits. By efficiently identifying the optimal design parameters for both circuits, the MDEA enables the reconstruction of each circuit within the Cadence environment. The voltage reference circuit successfully achieves a reference voltage of 550 mV, meeting the targeted specifications. However, it is worth noting that a variation of 8.18% in the reference voltage is observed due to temperature fluctuations ranging from −40°C to + 125°C. The designed ring oscillator (RO) circuit exhibits stable oscillation at a frequency of 2.001 GHz, accompanied by a phase noise of −87 dBc/Hz at an offset frequency of 1 MHz. Additionally, the power consumption of the RO circuit is measured at 71 μW. Notably, the SPICE simulation results demonstrate that the MDEA-based circuit design fulfills all the required performance parameters. Furthermore, the outcomes obtained through the MDEA approach surpass those reported in previous literature. Thus, the MDEA algorithm proves its efficacy in designing optimal RO and voltage reference circuits.

Data Availability

The data used to support the findings of this study are included within the article.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

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Copyright © 2023 Sandeep K. Dash et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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