A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

Figure 1

Nanodamascene process flow, illustrated for the fabrication of a SET device. Left: top down view. Right: cross section view. From top to bottom: trench formation in dielectric layer; metal line definition by lift-off or etching step; dielectric deposition by ALD or PVD; blanket metal layer deposition; CMP planarization step.