A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

Figure 2

In-process SETs fabrication micrographs: (a) trench formation in silicon oxide using ZEP520 resist; (b) patterning of the central island in TiN using HSQ resist; (c) top down view of completed device after the CMP step; (d) AFM view of the planarized surface.

(a)

(b)

(c)

(d)