Forming-Free Pt/Ti/AlO<sub>x</sub>/CeO<sub>x</sub>/Pt Multilayer Memristors with Multistate and Synaptic Characteristics

Wang, Wenqing; Zhao, Hongbin; Zhang, Baolin; Tu, Hailing

doi:https://doi.org/10.1155/2022/1370919

Journal of Nanomaterials

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Abstract Introduction Materials and Methods Results and Discussion Conclusions Data Availability Conflicts of Interest Acknowledgments Supplementary Materials References Copyright Related Articles

Research Article | Open Access

Volume 2022 | Article ID 1370919 | https://doi.org/10.1155/2022/1370919

Forming-Free Pt/Ti/AlO_x/CeO_x/Pt Multilayer Memristors with Multistate and Synaptic Characteristics

Wenqing Wang,^1,2Hongbin Zhao ,¹Baolin Zhang,²and Hailing Tu¹

Academic Editor: Shijun Liao

Received10 Dec 2021

Revised20 Aug 2022

Accepted08 Sept 2022

Published05 Oct 2022

Abstract

Due to their unique electrical performance and simple structure, memristors exhibit excellent application prospects for future information technology. In this work, we fabricated Pt/Ti/AlO_x/CeO_x/Pt memristors demonstrating electroforming-free bipolar resistive switching behavior with low operating voltage (−1 to 1 V), stable endurance, and retention. Space-charge limited conduction (SCLC) as well as the formation and rupture of conductive filaments are responsible for the resistive switching behavior. Increasing the magnitude of the RESET voltage could generate multistate resistive switching. We studied the synaptic characteristics of the device by obtaining multilevel conductance states and investigating the relationship between the device resistance, pulse amplitude, pulse width, and pulse number. By applying programmed pre and postsynaptic spiking pulses, spike-timing dependent plasticity was observed. This study shows that the device is suitable for multivalue storage and can be used as an electronic synapse device in artificial neural networks.

1. Introduction

The rapid development of complementary metal-oxide-semiconductor (CMOS) integrated circuit technology has brought the information age [1]. However, the emergence of memory walls has limited its further development [2–4]. In addition, artificial neural networks (ANNs) and large-scale calculations have brought significant challenges to current computing hardware [5–7]. The two-terminal structure and unique electrical characteristics of memristors have been widely studied [3, 8, 9]. The resistance of a memristor can be modulated by applying voltage or electron flux through it, where it will remain after electrical stimulation is stopped [8, 10–12]. Furthermore, the resistance of a memristor can be incrementally modulated by voltage pulses, offering significant potential for multilevel data storage [13–15]. Moreover, these multilevel conductances can also be used to simulate the weights of ANN, which has also been considered an ideal device for hardware neural networks (HNNs) [14, 16–18].

The resistance switching mechanism of the memristor primarily includes metal ion migration, oxygen vacancy migration [19], and charge effects [18, 20–25]. In the oxygen vacancy migration mechanism, the multilayer memristor generally exhibits better performance than the single-layer memristor due to the more controllable formation/breakage of conductive filaments (CF) between the electrodes [26]. CeO_x is a promising multilevel switching material because it can generate and modulate oxygen vacancies by changing the valence states of Ce cations (Ce³⁺ and Ce⁴⁺) under different applied electric fields [27–31]. Therefore, the resistance of the CeO_x layer can be modulated by applied voltages.

Recently, some studies have reported on the characteristics of cerium oxide-based memristors and their related multilayer film structures. Kim et al. reported on Pt/CeO₂/Pt devices with artificial synaptic characteristics, which exhibit polarity-dependent analog memristive switching [32]. Hsieh et al. reported on HfO_x/CeO_x bilayer memristors, which have forming-free, low-voltage, and analog characteristics [33]. In addition, Muhammad et al. demonstrated multilevel bipolar resistive switching characteristics in Ni/CeO_2−x/ITO/glass devices by controlling RESET voltage and current compliance [34]. However, the realization of both multivalue storage and use as an electronic synapse device based on the pulse voltage (less than 1 V in amplitude) of the CeO_x multilayer film device has not been reported. We observed that by rationally designing the device structure of multiple layers, memristors could exhibit better and more diverse performance [27, 28, 33, 35]. Compared to these studies [27–34], our study designed a Pt/Ti/AlO_x/CeO_x/Pt multilayer structure memristor that has a low working voltage and good working properties such as multivalued characteristics, neuroplasticity, and learning mechanism simulation. In this work, all characteristics of the Pt/Ti/AlO_x/CeO_x/Pt multilayer memristor were studied.

The innovation in this work consisted of the design of a ceria-based multilayer memristor device structure, which provided regulation and improvement to the performance of a single-layer ceria memristor. Compared to previous ceria-based memristors, the memristor designed in the present study exhibits a variety of multistate, synaptic and forming-free performance characteristics under a small operating voltage. This improves the usability and practicality of the ceria-based memristors. This multilayer memristor design method, based on a single functional layer, provides an ideal approach for the expansion and improvement of memristor performance.

This device has forming-free and multivalued characteristics by DC voltage sweep. Furthermore, the Pt/Ti/AlO_x/CeO_x/Pt device can also modulate the resistance based on the input pulse amplitude and emulate the STDP learning rule with good repeatability. The storage device based on Pt/Ti/AlO_x/CeO_x/Pt has the potential to be used for adaptive calculations in neuromorphic systems. Furthermore, we systematically explained the multivalue and synaptic characteristics of the device and reveal the relationship between the electrical performance and the conduction mechanism.

2. Materials and Methods

A JGP560C15 ultrahigh vacuum magnetron sputtering coating system was used to manufacture the device along chamber pressure below . A CeO_x layer (~50 nm) was deposited onto the Pt/Ti/SiO₂/Si substrates by radio frequency (RF) magnetron sputtering, and Ar and O₂ at a rate of 1 : 2 were used as the working gases. The chamber pressure was maintained at 2.5 Pa with an RF power value of 60 W. Then, an AlO_x layer (~50 nm) was deposited onto the CeO_x/Pt/Ti/SiO₂/Si substrate with high-purity Ar. The working pressure was maintained at 2.5 Pa with an RF power value of 60 W. Additionally, a Ti layer (~20 nm) was deposited onto the AlO_x/CeO_x/Pt/Ti/SiO₂/Si substrates by sputtering the high purity Ti target (99.99%) in high-purity Ar. The chamber pressure was maintained at 1 Pa with an RF power value of 60 W. Finally, the Pt top electrode with a diameter of ∼400 μm was deposited using a shadow mask. X-ray photoelectron spectroscopy (XPS, ESCALAB 250Xi) was used to analyze the composition of the multilayer structure, and the current-voltage (I-V) characterizations of the Pt/Ti/AlO_x/CeO_x/Pt devices were measured by a Keithley 4200 semiconductor parameter analyzer.

3. Results and Discussion

Figure 1(a) depicts the structure of the device consisting of the Ti insert layer, AlO_x/CeO_x switching layer, and Pt electrodes. We applied voltage to the top Pt electrode while the bottom Pt electrode was grounded. Figure 1(b) shows the Ce 3d levels of the CeO_x film, where the red line corresponds to the Ce⁴⁺ ions with peaks at 882 eV (v), 888.5 eV (v2), 897.9 eV (v3), 900.5 eV (u), 907 eV (u2), and 916.3 eV (u3). The blue line corresponds to the Ce³⁺ ions with peaks at 883.7 eV (v1) and 902.1 eV (u1). Symbol u and v represent the 3d_5/2 and 3d_3/2 spin-orbit components, respectively, [36]. This shows that Ce³⁺ and Ce⁴⁺ coexist in the CeO_x film, and the device contains some oxygen vacancies in the CeO_x film layer. The deconvoluted O 1 s in CeO_x is shown in Figure S3. These peaks are related to the oxygen vacancies, lattice oxygen, and surface oxygen species.

(a)

(b)

(c)

(d)

Figure 1(c) shows the I–V curve of the Pt/Ti/AlO_x/CeO_x/Pt device under direct current (DC) sweeping at room temperature, where no forming process was needed. The sweeping rate was 0.24 V/s; the sweeping step was 0.01 V, and the voltage-time curve of the DC sweep is shown in Figure S2 (a). The pristine device was in a high resistance state (HRS). Then, a positive sweep voltage was applied to the device with current compliance (I_cc) of 8 mA to prevent a dielectric breakdown. When the voltage reached 0.6 V, the current of the device suddenly increased to I_cc, and the device changed into the low resistance state (LRS), which is denoted as the SET process. The device remained in LRS when the sweep voltage decreased from 1 V to 0 V. When the voltage bias was swept from 0 V to −1 V, the cell transformed from LRS to HRS, and this process is called RESET. Then, a negative sweep voltage of −1 V →0 V was applied again, and the device remained in HRS. Resistive switching where the SET and RESET processes occur at opposite polarities and is considered as bipolar switching behavior. Figure 1(d) shows the retention characteristics of HRS and LRS measured at room temperature. The 0.01 V read voltage was applied every 1 s, and the resistance values of LRS and HRS were observed as stable over 2000 s. The DC I–V curve of the Pt/Ti/AlO_x/CeO_x/Pt device in 100 consecutive cycles is shown in Figure S1(a). The distribution of SET and RESET voltages of the Pt/Ti/AlO_x/CeO_x/Pt device is shown in Figure S1(b), and the mean and standard deviation for Vset and Vreset are shown in Figure S1(c). The cell to cell variation is shown in Figure S1(d). The device has a small operating voltage, as well as forming-free and retention characteristics, which can contribute to the decreased complexity of the peripheral circuit design.

To understand the conduction and switching mechanisms of the Pt/Ti/AlO_x/CeO_x/Pt device, the ln(|V|)–ln(|I|) characteristic curve was studied, and the fitted curves of the positive and negative sweep region are shown in Figure 2(a) and Figure 2(b). In LRS, we observed that Ohmic conductance best fit the curve in both the positive and negative bias voltage regions, which is usually observed in the conductive filament model. In HRS, the two fitted slopes suggest that the carrier transport mechanism in the HRS followed space-charge limited conduction (SCLC) model [30, 37–42]. SCLC has three different regions, the Ohmic region (I∝V), the modified Child’s law region (), and the trap-filled-limit (TFL) region (, ) in a high electric field. The Child’s law region can be described by [43] where is the dielectric constant; is the carrier mobility; is the density of states in the valence band; is the effective trapping potential; is the Boltzmann’s constant; is the temperature; is the number of traps, and is the effective film thickness.

(a)

(b)

(c)

According to the curve fitting and XPS analysis results, we determined the conduction and resistance switching mechanisms of the device. As shown in Figure 2(c), at first, the sweep voltage was small, and most of the electrons injected into the resistive switching layer were thermally generated electrons. The fitted slope was approximately 1.29. This I-V curve region corresponded to . As the positive voltage increased, the unfilled trap center was gradually occupied by electrons, and the slope of the fitted plot increased to 1.93 which corresponded to the region. When the applied voltage was sufficiently high, and most of the traps were completely occupied by electrons, the slope of the fitted plot increased to 2.83 which corresponded to the region. The fitting mechanism data (Ohmic and SCLC) are shown in Figure S4 (a–d) and Figure S5 (a–d).

When a sufficient internal electric field was generated, oxygen vacancy CFs were formed. Afterward, the resistance of the device abruptly switched from HRS to LRS. Due to the oxygen vacancy, CF has small resistance; the I-V curve region corresponded to . When a negative voltage was applied to the top Pt electrode, the CFs gradually broke, leading to the resistance switching from LRS to HRS. The HRS in the negative sweep region (from −1 V to 0 V) where the slope decreased from 3.66 to 1.66, and finally to 1.11, also followed SCLC model. In summary, the resistance switching of the device results from SCLC and the oxygen vacancy CFs mechanism. Because some oxygen vacancies formed after the device was fabricated, the device does not require the forming process.

Next, we studied the multilevel resistive switching on another Pt/Ti/AlO_x/CeO_x/Pt device. As Figure 3(a) shows the different RESET stop voltages (−0.6 V, −0.7 V, −0.8 V, −0.9 V, and −1 V) to achieve a five-level HRS. The reading voltage was 0.01 V, and the resistance was 94 Ω, 434 Ω, 865 Ω, 1357 Ω, and 2102 Ω, respectively. The controllability of the resistance during the reset process is found to be appropriate for multivalue storage. Figure 3(b) shows the resistance uniformity of the 5 resistance states in the 70 continuous cycles. Figure 3(c) shows the data retention performance of the Pt/Ti/AlO_x/CeO_x/Pt multilayer memristor with a 0.01 V read voltage. Moreover, this device can obtain different R_LRS by controlling different compliance currents. Figure S6 shows different Vreset limitations to control R_HRS and different compliance currents to control R_LRS.

(a)

(b)

(c)

The five-level HRS corresponds to the partial rupture of the multifilaments with increasing negative voltage in the multilayer film. As larger negative voltages were applied to the device, more filaments were ruptured and the device showed higher resistance states. A similar physical model was explained by Kim et al. [32]. This device is promising for high-density storage memory applications due to its reliable multilevel data storage ability.

Subsequently, we studied the synaptic weight modification of the device which is similar to biological synapses. As shown in Figure 4(a), at first, the resistance of the device was set to about 1000 Ω. Then, 11 pulses of 50 ms with the amplitudes of voltage consecutively increasing from 0.45 to 0.55 V with a step of 0.01 V were applied. With these positive voltage pulses, the resistance gradually decreased. 8 pulses of 50 ms with the amplitudes of voltage consecutively decreasing from −0.6 to −0.75 V with a step of 0.025 V were applied, and the resistance gradually increased. A read voltage of 0.01 V was used to measure its resistance state after each pulse voltage. The conductance can be adjusted repeatedly by applying pulse cycles composed of pulses with different amplitudes. The applied pulse cycle is shown in Figure S2(b). As shown in Figure 4(b), within the cycles of 500 pulses, the continuously adjustable conductance of the device shows good stability.

(a)

(b)

Furthermore, the relationships between device resistance modulation, pulse amplitude, pulse width, and pulse number were studied. As shown in Figures 5(a–d), the greater the amplitude and width of the pulse is, the greater modulation of device resistance is in both the depression and potentiation parts. However, when continuous pulses were applied to the device, the resistance of the device gradually decreased or increased, and finally reached a limit, where the greater the amplitude and width of the pulse is, the greater the limit is. Hence, each method for the modulation of device conductance has its corresponding limit. After reaching this limit, its conductive state will remain stable, which is similar to the phenomenon of biological synaptic saturation, and further research is needed [44].

(a)

(b)

(c)

(d)

Figure 5

(a) Device resistance modulation by applying 100 voltage pulses. (−0.6 V) with different pulse widths (5 ms, 50 ms, and 250 ms). (b) Device resistance modulation by applying 100 voltage pulses (50 ms) with various amplitudes (−0.6 V, −0.7 V, −0.8 V, and−0.9 V). (c) Device resistance modulation by applying 100 voltage pulses (0.45 V) with different pulse widths (5 ms, 50 ms, and 250 ms). (d) Device resistance modulation by applying 100 voltage pulses (50 ms) with various amplitudes (0.4 V, 0.45 V, and 0.5 V).

For biological synapses, the most important rule will be STDP [45–49]. Generally, STDP indicates that if the prespike precedes the postspike (); then, long-term potentiation (LTP) will occur, and synaptic weight (w) will increase [14]. If the prespike follows the postspike (), long-term depression (LTD) will happen and the synaptic weight (w) will decrease. At the same time, the smaller and the greater , where can be defined as _, and the range of follows (0, +∞) and (−1, 0).

As shown in Figure 6(a), the waveform was designed to generate the STDP phenomenon and is composed of continuous single pulses. The negative pulse occupied the first time slot, and then the positive pulse with reduced amplitude followed in the subsequent time slot. When the prespike and postspike overlapped, a programming pulse could be generated with an amplitude sufficient to modulate the resistance. The voltage dropped on the device is defined as the prespike voltage minus the postspike voltage. As the spike timing was tighter, the negative pulse would overlap the positive pulse with a larger amplitude, resulting in a larger resistance modulation. If the prespike preceded the postspike, a positive programming pulse (left in the Figure 6(a)) would be generated. Otherwise, a negative programming pulse would be generated (right in the Figure 6(a)). As shown in Figure 6(b), we simulated this STDP learning rule with this device. At and , LTP occurred; while for and , LTD occurred, and the spike timing was tighter, resulting in a larger resistance modulation. The experimental learning data for the STDP rule was well fitted to the exponential function, and fitting parameters are shown in Figure 6(b). where is the change in synaptic weights; is the scaling factor, and is the time constant. The characteristics of adjustable conductance, synaptic saturation, and simulating the STDP learning rules indicate that storage devices based on Pt/Ti/AlO_x/CeO_x/Pt have the potential to be used for adaptive calculations in neuromorphic systems.

(a)

(b)

In addition, the endurance and robustness of the Pt/Ti/AlO_x/CeO_x/Pt device need to be further optimized for commercial applications of multivalued and synaptic characteristics, according to Mario Lanza et al. [50]. In further experiments, we plan to insert a layer with good endurance performance or dope in the switching layer to effectively improve the tolerance of the device.

4. Conclusions

In this work, we fabricated a multilayer structure of Pt/Ti/AlO_x/CeO_x/Pt device. The SCLC and oxygen vacancy CFs mechanisms were used to explain the electrical characteristics of the device. There are several key advantages of this device: (i) this device is forming-free and has cycle-to-cycle as well as device-to-device consistency, which is beneficial to lowering the complexity of the circuit architecture; (ii) this device has nonvolatile and recyclable multivalued characteristics, which could address the major concern in the memory industry; (iii) this device has synaptic properties such as adjustable conductance, synaptic saturation, and simulating STDP learning rules, which has immense potential in artificial neuromorphic computing. All of these unique electrical performances suggest that the device has the potential to avoid the von Neumann bottleneck and shows great potential in both the emerging neuromorphic computation system and multivalue storage applications.

Data Availability

The data that support the findings of this study are available within the article and its supplementary material.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

Acknowledgments

This work was supported by Open Fund of Key Laboratory of New Processing Technology for Nonferrous Metal & Materials, Guangxi Key Laboratory of Optical and Electronic Materials and Devices, Guilin University of Technology (19AA-1).

Supplementary Materials

Figure S1 shows the endurance characteristic, the distribution of SET and RESET voltage, the standard deviation and mean for Vset and Vreset and cell to cell variation of the Pt/Ti/AlO_x/CeO_x/Pt device. Figure S2. shows the voltage-time curve of DC sweep and the pulse cycle curve of figure 4(a). Figure S3. shows the deconvolution of the O 1 s spectrum of CeO_x. Figure S4. shows the double logarithmic I-V characteristics of Pt/Ti/AlOx/CeOx/Pt device in positive bias. Figure S5. shows the double logarithmic I-V characteristics of Pt/Ti/AlOx/CeOx/Pt device in negative bias. Figure S6. shows the I-V sweep cruve of different Vreset limitations to control R_HRS and different compliance currents to control R_LRS, respectively. (Supplementary Materials)

References

P. Yao, H. Q. Wu, B. Gao et al., “Fully hardware-implemented memristor convolutional neural network,” Nature, vol. 577, no. 7792, pp. 641–646, 2020.
View at: Publisher Site | Google Scholar
P. Zheng, B. Sun, Y. Chen et al., “Photo-induced negative differential resistance in a resistive switching memory device based on BiFeO₃/ZnO heterojunctions,” Applied Materials Today, vol. 14, pp. 21–28, 2019.
View at: Publisher Site | Google Scholar
G. Zhou, Z. Ren, L. Wang et al., “Resistive switching memory integrated with amorphous carbon-based nanogenerators for self-powered device,” Nano Energy, vol. 63, article 103793, 2019.
View at: Publisher Site | Google Scholar
K. Berggren, Q. Xia, K. K. Likharev et al., “Roadmap on emerging hardware and technology for machine learning,” Nanotechnology, vol. 32, no. 1, article 012002, 2021.
View at: Google Scholar
J. H. Ryu, C. Mahata, and S. Kim, “Long-term and short-term plasticity of Ta₂O₅/HfO₂ memristor for hardware neuromorphic application,” Journal of Alloys and Compounds, vol. 850, no. 850, article 156675, 2021.
View at: Publisher Site | Google Scholar
H. Wang, L. Hu, and W. Han, “Resistive switching behavior, mechanism and synaptic characteristics in TiO₂ nanosheets grown on Ti plate by hydrothermal method,” Journal of Alloys and Compounds, vol. 854, no. 854, article 157200, 2021.
View at: Publisher Site | Google Scholar
L. Sun, G. Hwang, W. Choi et al., “Ultralow switching voltage slope based on two-dimensional materials for integrated memory and neuromorphic applications,” Nano Energy, vol. 69, p. 104472, 2020.
View at: Publisher Site | Google Scholar
S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, “Nanoscale memristor device as synapse in neuromorphic systems,” Nano Letters, vol. 10, no. 4, pp. 1297–1301, 2010.
View at: Publisher Site | Google Scholar
B. Sun, Y. Chen, M. Xiao et al., “A unified capacitive-coupled memristive model for the nonpinched current-voltage hysteresis loop,” Nano Letters, vol. 19, no. 9, pp. 6461–6465, 2019.
View at: Publisher Site | Google Scholar
J. Wang and F. Zhuge, “Memristive Synapses for Brain-Inspired Computing,” Advanced Materials Technologies, vol. 4, no. 3, article 1800544, 2019.
View at: Publisher Site | Google Scholar
A. R. Patil, T. D. Dongale, S. S. Nirmale, R. K. Kamat, and K. Y. Rajpure, “Bipolar resistive switching and memristive properties of sprayed deposited Bi₂WO₆ thin films,” Materials Today Communications, vol. 28, article 102621, 2021.
View at: Publisher Site | Google Scholar
C. C. Revadekar, A. V. Takaloo, S. P. Shinde et al., “Frugal discrete memristive device based on potassium permanganate solution,” Materials Research Express, vol. 8, no. 7, article 076304, 2021.
View at: Publisher Site | Google Scholar
C. Mahata, M. H. Kim, S. Bang et al., “SiO2layer effect on atomic layer deposition Al2O3-based resistive switching memory,” Applied Physics Letters, vol. 114, no. 18, article 182102, 2019.
View at: Publisher Site | Google Scholar
M. A. Zidan, J. P. Strachan, and W. D. Lu, “The future of electronics based on memristive systems,” Nature Electronics, vol. 1, no. 1, pp. 22–29, 2018.
View at: Publisher Site | Google Scholar
W. Ma, L. Liu, Y. Wang et al., “Multilevel resistive switching in HfOx/TiOx/HfOx/TiOx multilayer-based RRAM with high reliability,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3, Guilin, 2014.
View at: Google Scholar
Z. Zhou, C. Liu, W. Shen et al., “The characteristics of binary spike-time-dependent plasticity in HfO2-based RRAM and applications for pattern recognition,” Nanoscale Research Letters, vol. 12, no. 1, p. 244, 2017.
View at: Publisher Site | Google Scholar
Z. R. Wang, S. Joshi, S. E. Savel'ev et al., “Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing,” Nature Materials, vol. 16, no. 1, pp. 101–108, 2017.
View at: Publisher Site | Google Scholar
H. Zhang, C. Cheng, H. Zhang et al., “Physical mechanism for the synapse behaviour of WTiOx-based memristors,” Physical Chemistry Chemical Physics, vol. 21, no. 42, pp. 23758–23763, 2019.
View at: Publisher Site | Google Scholar
S. R. Patil, N. B. Mullani, B. B. Kamble et al., “Forming-free and multilevel resistive switching properties of hydrothermally synthesized hexagonal molybdenum oxide microrods,” Journal of Materials Science: Materials in Electronics, vol. 32, no. 9, pp. 12490–12502, 2021.
View at: Publisher Site | Google Scholar
D. Y. Guo, Z. P. Wu, L. J. Zhang et al., “Abnormal bipolar resistive switching behavior in a Pt/GaO_1.3/Pt structure,” Applied Physics Letters, vol. 107, no. 3, article 032104, 2015.
View at: Publisher Site | Google Scholar
P. C. Wang, P. G. Li, Y. S. Zhi et al., “Bias tuning charge-releasing leading to negative differential resistance in amorphous gallium oxide/Nb:SrTiO3heterostructure,” Applied Physics Letters, vol. 107, no. 26, article 262110, 2015.
View at: Publisher Site | Google Scholar
S. Gao, F. Zeng, M. J. Wang, G. Y. Wang, C. Song, and F. Pan, “Tuning the switching behavior of binary oxide-based resistive memory devices by inserting an ultra-thin chemically active metal nanolayer: a case study on the Ta2O5-ta system,” Physical Chemistry Chemical Physics, vol. 17, no. 19, pp. 12849–12856, 2015.
View at: Publisher Site | Google Scholar
G. Zhou, B. Sun, X. Hu et al., “Negative photoconductance effect: an extension function of the TiOx -based memristor,” Advanced Science, vol. 8, no. 13, article 2003765, 2021.
View at: Publisher Site | Google Scholar
C. Li, B. Zhang, Z. Qu et al., “Characterization of the inhomogeneity of Pt/CeOx/Pt resistive switching devices prepared by magnetron sputtering,” Nanotechnology, vol. 32, no. 14, article 145710, 2021.
View at: Publisher Site | Google Scholar
A. A. Gismatulin, V. A. Voronkovskii, G. N. Kamaev et al., “Electronic structure and charge transport mechanism in a forming-free SiOx-based memristor,” Nanotechnology, vol. 31, no. 50, article 505704, 2020.
View at: Publisher Site | Google Scholar
S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H. S. P. Wong, “An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2729–2737, 2011.
View at: Publisher Site | Google Scholar
M. Ismail, E. Ahmed, A. M. Rana et al., “Improved endurance and resistive switching stability in ceria thin films due to charge transfer ability of Al dopant,” ACS Applied Materials & Interfaces, vol. 8, no. 9, pp. 6127–6136, 2016.
View at: Publisher Site | Google Scholar
A. M. Rana, M. Ismail, T. Akber, M. Y. Nadeem, and S. Kim, “Transition from unipolar to bipolar, multilevel switching, abrupt and gradual reset phenomena in a TaN/CeO₂/Ti: /Pt memory devices,” Materials Research Bulletin, vol. 117, no. 117, pp. 41–47, 2019.
View at: Publisher Site | Google Scholar
H. Zheng, H. J. Kim, P. Yang et al., “Forming-free resistive switching characteristics of Ag/CeO2/Pt devices with a large memory window,” Semiconductor Science and Technology, vol. 32, no. 5, p. 055006, 2017.
View at: Publisher Site | Google Scholar
W. Q. Wang, B. L. Zhang, and H. B. Zhao, “Forming-free bipolar and unipolar resistive switching behaviors with low operating voltage in ag/Ti/CeO2/Pt devices,” Results in Physics, vol. 16, article 103001, 2020.
View at: Publisher Site | Google Scholar
P. Gao, Z. C. Kang, W. Y. Fu, W. L. Wang, X. D. Bai, and E. G. Wang, “Electrically driven redox process in cerium oxides,” Journal of the American Chemical Society, vol. 132, no. 12, pp. 4197–4201, 2010.
View at: Publisher Site | Google Scholar
H. J. Kim, H. Zheng, J. S. Park et al., “Artificial synaptic characteristics with strong analog memristive switching in a Pt/CeO2/Pt structure,” Nanotechnology, vol. 28, no. 28, article 285203, 2017.
View at: Publisher Site | Google Scholar
C. C. Hsieh, A. Roy, Y. F. Chang, D. Shahrjerdi, and S. K. Banerjee, “A sub-1-volt analog metal oxide memristive-based synaptic device with large conductance change for energy-efficient spike-based computing systems,” Applied Physics Letters, vol. 109, no. 22, article 223501, 2016.
View at: Publisher Site | Google Scholar
M. Ismail, A. Ahmad, K. Mahmood et al., “Room temperature deposited oxygen-deficient CeO_{2− _x_} layer for multilevel resistive switching memory,” Applied Surface Science, vol. 483, no. 483, pp. 803–810, 2019.
View at: Publisher Site | Google Scholar
W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, and H. Qian, “Improving analog switching in HfOx-Based resistive memory with a thermal enhanced layer,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1019–1022, 2017.
View at: Publisher Site | Google Scholar
P. Wang, S. Chen, S. Gao, J. Zhang, H. Wang, and Z. Wu, “Niobium oxide confined by ceria nanotubes as a novel SCR catalyst with excellent resistance to potassium, phosphorus, and lead,” Applied Catalysis B: Environmental, vol. 231, pp. 299–309, 2018.
View at: Publisher Site | Google Scholar
Q. Zuo, S. Long, Q. Liu et al., “Self-rectifying effect in gold nanocrystal-embedded zirconium oxide resistive memory,” Journal of Applied Physics, vol. 106, no. 7, article 073724, 2009.
View at: Publisher Site | Google Scholar
C. Chen, Y. C. Yang, F. Zeng, and F. Pan, “Bipolar resistive switching in cu/AlN/Pt nonvolatile memory device,” Applied Physics Letters, vol. 97, no. 8, article 083502, 2010.
View at: Publisher Site | Google Scholar
Y. Chen, H. Song, H. Jiang et al., “Reproducible bipolar resistive switching in entire nitride AlN/n-GaN metal-insulator-semiconductor device and its mechanism,” Applied Physics Letters, vol. 105, no. 19, article 193502, 2014.
View at: Publisher Site | Google Scholar
T. Guo, B. Sun, Y. Zhou, H. Zhao, M. Lei, and Y. Zhao, “Overwhelming coexistence of negative differential resistance effect and RRAM,” Physical Chemistry Chemical Physics, vol. 20, no. 31, pp. 20635–20640, 2018.
View at: Publisher Site | Google Scholar
W. Wang, Y. Li, W. Yue et al., “Study on multilevel resistive switching behavior with tunable ON/OFF ratio capability in forming-free ZnO QDs-based RRAM,” IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4884–4890, 2020.
View at: Publisher Site | Google Scholar
X. Hu, W. Wang, B. Sun, Y. Wang, J. Li, and G. Zhou, “Refining the negative differential resistance effect in a TiO_x-based memristor,” Journal of Physical Chemistry Letters, vol. 12, no. 22, pp. 5377–5383, 2021.
View at: Publisher Site | Google Scholar
G. Zhou, Z. Ren, L. Wang, B. Sun, S. Duan, and Q. Song, “Artificial and wearable albumen protein memristor arrays with integrated memory logic gate functionality,” Materials Horizons, vol. 6, no. 9, pp. 1877–1882, 2019.
View at: Publisher Site | Google Scholar
B. A. Olshausen, “Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems: Peter Dayan and LF Abbott MIT Press, Cambridge, $50.00 ISBN: 0-262-04199-5 460 pages,” The Journal of Cognitive Neuroscience, vol. 15, no. 1, p. 154, 2003.
View at: Publisher Site | Google Scholar
Y. Li, Y. P. Zhong, L. Xu et al., “Ultrafast synaptic events in a chalcogenide memristor,” Scientific Reports, vol. 3, no. 1, 2013.
View at: Publisher Site | Google Scholar
R. Pan, J. Li, F. Zhuge et al., “Synaptic devices based on purely electronic memristors,” Applied Physics Letters, vol. 108, no. 1, article 013504, 2016.
View at: Publisher Site | Google Scholar
M. J. Yu, K. R. Son, A. C. Khot et al., “Three Musketeers: demonstration of multilevel memory, selector, and synaptic behaviors from an Ag-GeTe based chalcogenide material,” Journal of Materials Research and Technology, vol. 15, no. 15, pp. 1984–1995, 2021.
View at: Publisher Site | Google Scholar
T. D. Dongale, A. C. Khot, A. V. Takaloo, and T. G. Kim, “Facile synthesis of nickel cobaltite quasi-hexagonal nanosheets for multilevel resistive switching and synaptic learning applications,” NPG Asia Materials, vol. 13, no. 1, pp. 1-2, 2021.
View at: Publisher Site | Google Scholar
A. R. Patil, T. D. Dongale, R. K. Kamat, and K. Y. Rajpure, “Spray pyrolysis deposited iron tungstate memristive device for artificial synapse application,” Materials Today Communications, vol. 29, article 102900, 2021.
View at: Publisher Site | Google Scholar
M. Lanza, H. S. Wong, E. Pop et al., “Recommended methods to study resistive switching devices,” Advanced Electronic Materials, vol. 5, no. 1, article 1800143, 2019.
View at: Publisher Site | Google Scholar

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Copyright © 2022 Wenqing Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Journal of Nanomaterials

Forming-Free Pt/Ti/AlOx/CeOx/Pt Multilayer Memristors with Multistate and Synaptic Characteristics

Abstract

1. Introduction

2. Materials and Methods

3. Results and Discussion

4. Conclusions

Data Availability

Conflicts of Interest

Acknowledgments

Supplementary Materials

References

Copyright

Forming-Free Pt/Ti/AlO_x/CeO_x/Pt Multilayer Memristors with Multistate and Synaptic Characteristics