A Smart Memory Controller for System on Chip-Based Devices

Table 1

Signal description of memory controller for mobile SoC.

Pin	Description
rd	This signal enables the read operation when MAC wants to read data from FIFO.
rd_data	The data bus, which holds data, is read from FIFO to write into the memory through the state machine.
full	This input indicates to the MAC state machine about FIFO-full status.
empty	This input indicates that FIFO is empty to the MAC state machine, with no further data available to read.
ptr	There are two FIFO pointers to indicate reading and writing location and decide between empty and full status.
wr	wr is a write-enabled signal to memory, indicating writing operation.
addr	Addr signal indicates the exact location of memory to write/read data from or into it.
Data	It is a data bus that carries data to write into and read from memory.
rd	Read enable to indicate read operations from memory.
fifo_wr	Enable signal from MAC state machine to write into the FIFO.
fifo-rd	Request from the peripheral to read data from FIFO.
Data-rd	Data bus carrying the data read from FIFO for any external device.