A Smart Memory Controller for System on Chip-Based Devices

Table 5

Data transfer rate for the proposed MAC and other existing methods.

Design	Max frequency (MHz)	Mega cycles per sec	Transfer rate (Mbytes/sec)
Proposed DMA	350	350	1400
DMA [30]	320	320	1200
DMA [31]	320	320	1200
DMAC [32]	250	250	1000
DMA [33]	250	250	1000