Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

<table class="table-group" id="tab5"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td class="align_left"> </td><td class="align_center" colspan="2">Number of nodes</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td class="align_left" rowspan="2">8-point DCT</td><td class="align_center" colspan="2">42</td></tr><tr><td class="align_center">16 multiplication operations</td><td class="align_center">26 addition operations</td></tr><tr><td class="align_left" rowspan="2">16-point DCT</td><td class="align_center" colspan="2">224</td></tr><tr><td class="align_center">128 multiplication operations</td><td class="align_center">96 addition operations</td></tr><tr><td class="align_left">H.264</td><td class="align_center" colspan="2">28</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

The characterization of each application.

Journal of Optimization

tab5

Table 5

Table 5: Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System 