Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Table 6

Design result provided by our algorithm.

8-point DCT	Number of partitions		458
	Best partition	Hardware	12 operations of (×)	19 operations of (+)
		Software	4 operations of (×)	7 operations of (+)
	Total power consumed (mW)		82.35
	The system’s latency (ns)		453
16-point DCT	Number of partitions		12512
	Best partition	Hardware	68 operations of (×)	91 operations of (+)
		Software	60 operations of (×)	5 operations of (+)
	Total power consumed (mW)		525.876
	The system’s latency (ns)		2780
H.264	Number of partitions		24
	Total power consumed (W)		6.850
	The system’s latency (ns)		1530