FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

Table 2

Summary of device utilization as generated by the Xilinx tool.

Logic utilization	Used	Available	Utilization
Total number of slice registers	2,471	4,896	50%
Number of 4 input LUTs	2,481	4,896	50%
Number of occupied slices	2,389	2,448	97%
Total number of 4 input LUTs	2,574	4,896	52%
Number of bonded IOBs	8	92	8%
Number of BUFGMUXs	2	24	8%