FPGA Implementation of a Single Step MFCV Estimator Based on EMG in Diabetic Neuropathy

Table 1

Processor-system level design features.

Type		Name	Description
IN	4	EMG	4 EMG from 2 surface electrodes on the right leg and 2 surface electrodes on the left one
OUT	2	MFCV	2 MFCV values associated to the right and left leg, derived according to (1) from the estimation
SYS	1	Clk_50MHz	FPGA embedded 50 MHz internal clock
SYS	1	Clk_8MHz	8 MHz system clock, PLL derived from Clk_50MHz.
SYS	1	Clk_2kHz	2 kHz system clock for ADC management