[Retracted] Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Figure 13

Throughput under URT. (a) FIR vs. throughput with two VCs, (b) FIR vs. throughput with four VCs, and (c) FIR vs. throughput with eight VCs, respectively.

(a)

(b)

(c)