An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

Algorithm 6

PACKAGE VHDLFUNPACKAGE IS

PROCEDURE MOVB(CONSTANT C1: IN INTEGER RANGE 255 DOWNTO 0;

         SIGNAL SOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

PROCEDURE ADDB(SIGNAL S1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

         SIGNAL S2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

         SIGNAL SOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END VHDLFUNPACKAGE;

PACKAGE BODY VHDLFUNPACKAGE IS

PROCEDURE MOVB(CONSTANT C1: IN INTEGER RANGE 255 DOWNTO 0;

         SIGNAL SOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) IS

    BEGIN

       SOUT <= CONV_STD_LOGIC_VECTOR(C1, 8);

    END PROCEDURE MOVB;

PROCEDURE ADDB(SIGNAL S1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

         SIGNAL S2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

         SIGNAL SOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) is

    BEGIN

       SOUT <= S1 + S2;

    END PROCEDURE ADDB;

END VHDLFUNPACKAGE;