An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

Figure 3

The transformation process from an AOV graph to an AND-OR tree.

(a) The original AOV graph with null AND-OR tree(s)

(b) Results of first stage AND-translation: the constructed AND-subtrees and the reduced AOV graph

(c) Results of second stage OR-translation: the constructed OR-subtree and the reduced AOV graph

(d) Results of third stage AND-translation: the constructed final AND-tree and the reduced AOV graph