An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static-preview.hindawi.com/articles/mpe/volume-2015/530586/figures/530586.fig.004a.svgz" name="530586.fig.004a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Source LD</td></tr><tr class="fig-image" id="b"><td><object data="https://static-preview.hindawi.com/articles/mpe/volume-2015/530586/figures/530586.fig.004b.svgz" name="530586.fig.004b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Associated AOV graph</td></tr></table>

<div>A more complicated example: source LD and its AOV graph.</div>

Mathematical Problems in Engineering

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Figure 4

Figure 4: An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams 