An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

Figure 5

AND-OR-tree construction for the complicated example: logics performed by the algorithm.

(a) The constructed OR-subtree from Figure 4(b)

(b) The reduced AOV graph of Figure 4(b) after the OR-subtree is constructed in (a)

(c) The constructed OR-subtree from (b)

(d) The reduced AOV graph of (b) after the OR-subtree is constructed in (c)

(e) The final AND-tree (with a null AOV graph which is not shown)