Sparse Cholesky Factorization on FPGA Using Parameterized Model

<div>Nonzeros pattern of <svg height="8.79011pt" id="M186" style="vertical-align:-0.04980946pt" version="1.1" viewbox="-0.0498162 -8.7403 7.2895 8.79011" width="7.2895pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M512 180C494 129 475 97 457 77C433 50 397 43 354 43C323 43 297 45 279 52C259 61 255 78 255 125V516C255 602 264 608 340 615V650H35V615C111 608 121 602 121 516V133C121 48 111 42 24 35V0H511C519 27 540 126 548 169L512 180Z" id="g13-74"></path></g></svg> and its elimination tree.</div>

Mathematical Problems in Engineering

Sparse Cholesky Factorization on FPGA Using Parameterized Model

Figure 3