A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Table 2

Comparison of post layout simulation results between existing and modified FA at 1.1V,27°C temp.

Scheme	Average Power (W)	Delay (pS)	PDP (aJ)	Leakage power(pW)	GBN(V)
Existing FA circuit
Conv_adder	12.2	322	3928	180	890
MA1 [19]	10	398	3980	94	856
MA2 [19]	8.1	368	2980	81	791
MA3 [19]	7.8	277	2160	84	753
MA4 [19]	9.2	362	3330	82	808
Imprecise_adder_1 [18]	7.7	361	2780	65	732
Imprecise adder_2[18]	11.8	360	4248	149	879
Inexact_adder_2017 [20]	7.5	361	2707	461	541
FA (hybrid_pass_logic) [21]	11	879	9669	636	587
Modified approximate FA
MMA1	9.8	479	4694	47	191
MMA2	8.0	408	3264	37	146
MMA3	7.7	316	2433	34	145
MMA4	9.1	325	2957	38	205