Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 1

Theoretical cache and TLB hit rate for row-directional access of a large-sized 2D array of double-precision floating-point operations.

	Row-major	Z-Morton order	Column-major
32-byte cache line	75%	50%	0%
64-byte cache line	87.5%	64.6%	0%
128-byte cache line	93.8%	75%	0%
4 KB page	99.8%	95.6%	0%
8 KB page	99.9%	96.9%	0%