Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 10

Execution time evaluation.

Matrix size	Conventional access	Parallel access	C/P
128	47 × 10^5	15 × 10^5	3
500	30 × 10^7	98 × 10^6	3
512	32 × 10^7	10 × 10^7	3
1000	23 × 10^8	78 × 10^7	3
1024	25 × 10^8	80 × 10^7	3
2000	19 × 10^9	62 × 10^8	3
2048	20 × 10^9	66 × 10^8	3