Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 2

Theoretical cache and TLB hit rate for column-directional access of a large-sized 2D array of double-precision floating-point operations.

	Row-major	Z-Morton order	Column-major
32-byte cache line	0%	50%	75%
64-byte cache line	0%	64.6%	87.5%
128-byte cache line	0%	75%	93.8%
4 KB page	0%	95.6%	99.8%
8 KB page	0%	96.9%	99.9%