Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 3

Theoretical cache and TLB hit rate for MM with double-precision floating-point operations.

	Row-major	Proposed layout	Column-major
64-byte cache line	48.4%	95.3%	48.4%
4 KB page	99.8%	96.9%	0%
4 KB page	0%	93.8%	99.8%

: row-directional access and : column-directional access.