Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 4

Theoretical cache and TLB hit rate for MM with single-precision floating-point operations.

	Row-major	Proposed layout	Column-major
64 byte cache line	48.4%	96.9%	48.4%
4 KB page	99.8%	93.8%	0%
4 KB page	0%	96.9%	99.8%

: row-directional access and : column-directional access.