Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 5

Chip specification.

Technology	40 nm	SRAM Macro area (tag)	0.68 mm^2
Clock frequency	250 MHz	SRAM Macro area (data)	3.44 mm^2
Chip size	5 × 5 mm^2	Total SRAM Macro area	4.12 mm^2
Aspect ratio	1.0	Data path logic scale	163654
Voltage supply	1.8 V	Peripheral circuit scale	35836

Number of NAND gate equivalents.