Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 7

Hardware scale for the 2-way set associative cache (number of NAND gate equivalents).

		64-byte cache line, 2-way
	Cache memory	Non-ATSRA	ATSRA
Peripheral circuit scale	Conventional	17860	17860
	Proposed	35836	32847
	P/C	2.00	2.00
Tag memory scale	Conventional	26360	26360
	Proposed	26360 × 4	26360
	P/C	4.00	1.00
Data memory scale	Conventional	338460	338460
	Proposed	338460	338460
	P/C	1.00	1.00
Entire cache scale	Conventional	382680	382680
	Proposed	479736	397667
	P/C	1.25	1.04