Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility

Table 9

Processor and memory hierarchy configuration [17].

	Instr.Fetch Queue	4
CPU	Instr.Issue	4-way out-of-order
	Branch Predictor	Bimod, 2 K entry BTB
	Data L1 Cache	32 Kbytes, 8-way, 64-byte cache line
Cache	Unified L2 cache	256 Kbytes, 8-way, 64-byte cache line
	Latency (cycles)	L1 hit: 1, L2 hit: 6, Memory: 30
TLB	DTLB	4 Kbytes page size, Hit: 1, Miss: 8