Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Table 2

Area reduction of the proposed FI function implemented on Xilinx Virtex-7.

Method	Ftns	LUTs				Area (slices)	% reduction
		2-1	3-1	4-1	5-1		With respect to [10]	With respect to [12]
Prop.	S9-1	—	—	3	6	27	66.7	41.3
	S9-2	—	—	6	3
	S9-3	—	—	6	3
	S9-4	—	—	9	—
	S9-5	—	—	4	5
	S9-6	—	—	9	—
	S9-7	—	1	6	2
	S9-8	—	—	9	—
	S7-1	—	—	1	6
	S7-2	—	—	6	1
	S7-3	—	—	6	1
	S7-4	—	—	—	7
	S7-5	7	—	—	—
	FI	7	1	65	34
[10]	FI	—				81
[12]	FI	—		—		46