Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Figure 10

(a) The input return loss (S11), insertion loss (S12), and output return loss (S22) power-divider circuit. (b) The input-referred 1 dB compression point. (c) The input reflection loss (S11). (d) The output gain (S21). (e) The power-added efficiency (PAE). (f) Validated software results with yellow line showing input noise and red showing the output noise. (g) Harmonic content and power contours.

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