Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Figure 3

(a) Impedance matching through the Smith chart for power combiner lumped parameters and (b) power divider lumped parameters. (c) Wilkinson power divider and (d) power combiner using equivalent RLC model.

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(b)

(c)

(d)