Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

<div>(a) The transient state before the interstage capacitor and (b) the transient state after the interstage capacitor of the main amplifier. (c) The result before the interstage state of the peaking amplifier and (d) its effect after the interstage capacitor as input power reaches −7 dBm.</div>

Mathematical Problems in Engineering

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Figure 5

Figure 5: Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology 