Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

<div>Comparative change in input vs. output noise in <svg height="14.0226pt" id="M63" style="vertical-align:-2.1506pt" version="1.1" viewbox="-0.0498162 -11.872 45.9007 14.0226" width="45.9007pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M524 0V26C466 32 460 36 460 104V297C460 393 411 449 331 449C302 449 276 437 248 419C223 402 201 387 181 372V451C137 432 90 420 42 411V388C96 378 102 374 102 310V104C102 38 97 33 29 26V0H246V26C187 32 181 36 181 104V339C211 365 250 390 290 390C357 390 381 345 381 276V109C381 40 374 32 315 26V0H524Z"></path></g><g transform="matrix(.013,0,0,-0.013,5.911,0)"><path d="M687 650H462V622C543 612 549 605 530 547C498 447 422 252 372 126H370C302 298 229 492 204 563C188 607 191 615 262 622V650H17V622C77 616 93 608 122 534C180 389 262 172 329 -11H360C436 196 541 450 568 516C606 605 619 614 687 622V650Z"></path></g><g transform="matrix(.013,0,0,-0.013,15.11,0)"><path d="M368 703H309L44 -163H104L368 703Z"></path></g><g transform="matrix(.013,0,0,-0.013,20.472,-1.631)"><path d="M782 731H740L476 -79H474L280 352L133 274L151 239L242 286L473 -219L782 731Z"></path></g><rect height="0.65243" width="15.3453" x="30.4408" y="-11.1697"></rect><g transform="matrix(.013,0,0,-0.013,30.441,0)"><path d="M729 650H468V622C546 615 554 610 554 527V365H213V527C213 610 221 616 297 622V650H38V622C120 616 128 611 128 527V123C128 39 120 34 40 28V0H303V28C221 34 213 40 213 123V322H554V123C554 39 546 34 460 28V0H728V28C647 34 639 39 639 123V527C639 610 647 615 729 622V650Z"></path></g><g transform="matrix(.013,0,0,-0.013,40.268,0)"><path d="M387 138L374 114C336 54 316 33 240 33H141C223 167 303 295 385 423L379 437H149C112 437 100 443 94 458H73C65 415 50 352 39 314L64 305L78 332C106 388 119 403 191 403C214 403 246 403 280 403C198 270 117 142 31 15L38 0H367C382 40 399 86 413 125L387 138Z"></path></g></svg> from 2.3 GHz to 2.6 GHz range.</div>

Mathematical Problems in Engineering

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Figure 7

Figure 7: Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology 