Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Figure 8

(a) The comparison of PAE to the input power and (b) the comparison of PAE to the output power. (c) Proof of the DC power consumption at a maximum level of 2.1 mW.

(a)

(b)

(c)