Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Table 1

Performance comparison of the proposed PA.

Specification	This work	[28]	[29]	[30]	[31]	[32]
Technology	65 nm	130 nm	40 nm	65 nm	180 nm	90 nm
Year	2021	2020	2019	2018	2017	2013
IEEE standard	802.15.4	802.15.4	802.15.6	802.15.4	802.15.1	802.15.4
Frequency	2.4 GHz	2.4 GHz	2.4 GHz	2.4 GHz	2.4 GHz	2.4 GHz
DC power consumption	2.1 mW	4.7 mW	1.5 mW	1.9 mW	10 mW
DC current consumption	1.22 mA	—	—			9.2 mA
Supply voltages	1.2 volts	1.2 volts	0.9 volts	1 volt		1.2 volts
IIP3		−12 dBm
Output power	2 dBm	0 dBm	−3.3 dBm	−3 dBm	5 dBm	0 dBm–4 dBm
1 dB compression point	4.1 dBm	−1.36 dBm	—	—	—	—
Input return loss (S11)	−13.1 dB	−10.3 dB	—	—	—	—
Gain (S21)	10.3 dB	—	—	—	8 dB	—
General class of PA	Doherty PA with fixed interstage capacitances	Class AB with current re-use	Switched capacitor digital PA (SCDPA)	PA-ADPLL all digital scaling	—	Load push-pull
			All digital scaling
Efficiency	29.85%	27%	39%	—	16%	—