Automatic Arrhythmia Detection Based on the Probabilistic Neural Network with FPGA Implementation

Table 2

Device utilization analysis of FPGA implementation of NN-based ECG classification.

Logic utilization	Used	Available	Utilization (%)
Number of slice register	1925	126800	1.5
Number of fully used LUT-FF pairs	0	1	0
Number of bonded IOBs	187	210	89
Number of BUFG/BUFGCTRLs	1	32	3
Time consumption	17 sec
Consumed on-chip power	25 mW