[Retracted] Investigation on the Status Quo of Students’ Physical Fitness Based on Wireless Communication Networks and Analysis of Influencing Factors

Table 2

Mainstream SoC chip comparison.

Chip type	Altera SoC FPGA	Zynq-7000	SmarFusion2
CPU	ARM cortex-A9	ARM cortex-A9	ARM cortex-M3
Maximum processor frequency	1 GHz	1 GHz	166 MHz
Level 1 cache	Both data and instruction cache 32 Kb	Both data and instruction cache 32 Kb	No data cache 32 Kb indicating cache
Level 2 cache	515 Kb	515 Kb	Not support
Logical resource	470 Kb	450 Kb	150 Kb
Katagami RAM	65 Kb	256 Kb	65 Kb
Interface clock	530 Kb	530 Kb	330 Kb