Encoding Test Pattern of System-on-Chip (SOC) Using Annular Scan Chain

Table 2

Experimental results.

Experimental circuit	FDR	ALT-FDR	EFDR	9C	BM	RL-HC	SHC	VIHC	GOLOMB	Proposed scheme
s5378	47.98	50.77	53.67	51.64	54.98	53.75	55.10	51.52	37.11	74.3
s9234	43.61	44.96	48.66	50.91	51.19	47.59	54.20	54.84	45.25	59.6
s13207	81.30	80.23	82.49	82.31	84.89	82.51	77.00	83.21	79.74	88.47
s15850	66.21	65.83	68.66	66.38	69.49	67.34	66.00	60.68	62.82	73.94
s38417	43.37	60.55	62.02	60.63	59.39	64.17	59.00	54.51	28.37	63.1
s38584	60.93	61.13	64.28	65.53	66.86	62.40	64.10	56.97	57.17	69.72
Average	60.01	60.58	63.55	63.35	65.48	62.72	63.28	61.44	56.42	71.52